MPAMF_PRI_IDR, MPAM Priority Partitioning Identification Register
The MPAMF_PRI_IDR characteristics are:
Purpose
The MPAMF_PRI_IDR is a 32-bit read-only register that indicates which MPAM priority partitioning features are present on this MSC. MPAMF_PRI_IDR_s indicates priority partitioning features accessed from the Secure MPAM feature page. MPAMF_PRI_IDR_ns indicates priority partitioning features accessed from the Non-secure MPAM feature page.
Configuration
The power domain of MPAMF_PRI_IDR is IMPLEMENTATION DEFINED.
This register is present only when MPAMF_IDR.HAS_PRI_PART == 1. Otherwise, direct accesses to MPAMF_PRI_IDR are RES0.
Attributes
MPAMF_PRI_IDR is a 32-bit register.
Field descriptions
The MPAMF_PRI_IDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | DSPRI_WD | RES0 | DSPRI_0_IS_LOW | HAS_DSPRI | RES0 | INTPRI_WD | RES0 | INTPRI_0_IS_LOW | HAS_INTPRI |
Bits [31:26]
Reserved, RES0.
DSPRI_WD, bits [25:20]
Number of implemented bits in the downstream priority field (DSPRI) of MPAMCFG_PRI.
If HAS_DSPRI == 1, this field must contain a value from 1 to 32, inclusive.
If HAS_DSPRI == 0, this field must be 0.
Bits [19:18]
Reserved, RES0.
DSPRI_0_IS_LOW, bit [17]
Indicates whether 0 in MPAMCFG_PRI.DSPRI is the lowest or the highest priority.
DSPRI_0_IS_LOW | Meaning |
---|---|
0b0 |
In the MPAMCFG_PRI.DSPRI field, a value of 0 means the highest priority. |
0b1 |
In the MPAMCFG_PRI.DSPRI field, a value of 0 means the lowest priority. |
HAS_DSPRI, bit [16]
Indicates that this MSC implements the DSPRI field in the MPAMCFG_PRI register.
HAS_DSPRI | Meaning |
---|---|
0b0 |
This MSC supports priority partitioning, but does not implement a downstream priority (DSPRI) field in the MPAMCFG_PRI register. |
0b1 |
This MSC supports downstream priority partitioning and implements the downstream priority (DSPRI) field in the MPAMCFG_PRI register. |
Bits [15:10]
Reserved, RES0.
INTPRI_WD, bits [9:4]
Number of implemented bits in the internal priority field (INTPRI) in the MPAMCFG_PRI register.
If HAS_INTPRI == 1, this field must contain a value from 1 to 32, inclusive.
If HAS_INTPRI == 0, this field must be 0.
Bits [3:2]
Reserved, RES0.
INTPRI_0_IS_LOW, bit [1]
Indicates whether 0 in MPAMCFG_PRI.INTPRI is the lowest or the highest priority.
INTPRI_0_IS_LOW | Meaning |
---|---|
0b0 |
In the MPAMCFG_PRI.INTPRI field, a value of 0 means the highest priority. |
0b1 |
In the MPAMCFG_PRI.INTPRI field, a value of 0 means the lowest priority. |
HAS_INTPRI, bit [0]
Indicates that this MSC implements the INTPRI field in the MPAMCFG_PRI register.
HAS_INTPRI | Meaning |
---|---|
0b0 |
This MSC supports priority partitioning, but does not implement the internal priority (INTPRI) field in the MPAMCFG_PRI register. |
0b1 |
This MSC supports internal priority partitioning and implements the internal priority (INTPRI) field in the MPAMCFG_PRI register. |
Accessing the MPAMF_PRI_IDR
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_PRI_IDR is read-only.
MPAMF_PRI_IDR must be readable from the Non-secure and Secure MPAM feature pages.
MPAMF_PRI_IDR is permitted to have the same contents when read from either the Secure and Non-secure MPAM feature pages unless the register contents is different for Secure and Non-secure versions, when there must be separate registers in the Secure (MPAMF_PRI_IDR_s) and Non-secure (MPAMF_PRI_IDR_ns) MPAM feature pages.
MPAMF_PRI_IDR can be accessed through the memory-mapped interfaces:
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0048 | MPAMF_PRI_IDR_s |
Accesses on this interface are RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x0048 | MPAMF_PRI_IDR_ns |
Accesses on this interface are RO.