PMPIDR2, Performance Monitors Peripheral Identification Register 2
The PMPIDR2 characteristics are:
Provides information to identify a Performance Monitor component.
For more information see 'About the Peripheral identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).
It is IMPLEMENTATION DEFINED whether PMPIDR2 is implemented in the Core power domain or in the Debug power domain.
Implementation of this register is OPTIONAL.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMPIDR2 is a 32-bit register.
The PMPIDR2 bit assignments are:
REVISION, bits [7:4]
Part major revision. Parts can also use this field to extend Part number to 16-bits.
JEDEC, bit 
RAO. Indicates a JEP106 identity code is used.
DES_1, bits [2:0]
Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.
Accessing the PMPIDR2
PMPIDR2 can be accessed through the external debug interface:
This interface is accessible as follows:
- When ARMv8.3-DoPD is not implemented or IsCorePowered() accesses to this register are RO.
- Otherwise accesses to this register generate an error response.