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PMVIDSR, VMID Sample Register

The PMVIDSR characteristics are:


Contains the sampled VMID value that is captured on reading PMPCSR[31:0].


PMVIDSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

This register is present only when ARMv8.2-PCSample is implemented. Otherwise, direct accesses to PMVIDSR are RES0.


Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.

If EL2 is not implemented, this register is RES0.


PMVIDSR is a 32-bit register.

Field descriptions

The PMVIDSR bit assignments are:


Bits [31:16]

Reserved, RES0.

VMID, bits [15:0]

VMID sample. The VMID associated with the most recent PMPCSR sample.

  • If EL2 is implemented and is using AArch64, then the VMID is held in VTTBR_EL2.VMID.
  • If EL2 is implemented and is using AArch32, then the VMID is held in VTTBR.VMID.
  • This field is set to an UNKNOWN value if any of the following apply:
    • PMPCSR.NS == 0.
    • PMPCSR.EL == 0b10.
    • PMPCSR.NS == 1, PMPCSR.EL == 0b00, EL2 is using AArch64, HCR_EL2.E2H == 1, and HCR_EL2.TGE == 1.
  • If EL2 is not implemented, then this field is RES0.
  • If 16-bit VMIDs are not supported, PMVIDSR.VMID[15:8] is RES0.
  • If 16-bit VMIDs are supported, but VTTBRx.VMID[15:8] are not used, PMVIDSR.VMID[15:8] is set to RES0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the PMVIDSR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile

PMVIDSR can be accessed through the external debug interface:


This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.