TRCLSR, Lock Status Register
The TRCLSR characteristics are:
Purpose
Indicates whether the Software Lock is implemented, and the current status of the Software Lock.
For additional information see the CoreSight Architecture Specification.
Configuration
This register is present only when ETE is implemented. Otherwise, direct accesses to TRCLSR are RES0.
There are no configuration notes.
Attributes
TRCLSR is a 32-bit register.
Field descriptions
The TRCLSR bit assignments are:
Bits [31:3]
Reserved, RES0.
nTT, bit [2]
Software lock size.
This bit reads as 0b0.
SLK, bit [1]
The current Software Lock status.
SLK | Meaning |
---|---|
0b0 |
Software Lock is unlocked. |
0b1 |
Software Lock is locked. Writes to the other registers in this component, except for the TRCLAR, are ignored. |
This bit reads as zero.
SLI, bit [0]
Indicates whether the Software Lock is implemented.
SLI | Meaning |
---|---|
0b0 |
Software Lock is not implemented. Writes to the TRCLAR are ignored. |
0b1 |
Software Lock is implemented. |
This bit reads as zero.
Accessing the TRCLSR
External debugger accesses to this register are unaffected by the OS Lock.
TRCLSR can be accessed through the external debug interface:
Component | Offset |
---|---|
ETE | 0xFB4 |
This interface is accessible as follows:
- When !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.