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TRCPIDR3, Peripheral Identification Register 3

The TRCPIDR3 characteristics are:


Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.


This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR3 are RES0.

There are no configuration notes.


TRCPIDR3 is a 32-bit register.

Field descriptions

The TRCPIDR3 bit assignments are:


Bits [31:8]

Reserved, RES0.

REVAND, bits [7:4]


Component minor revision. TRCPIDR2.REVISION and TRCPIDR3.REVAND together form the revision number of the component, with REVISION being the most significant part and REVAND the least significant part. When a component is changed, REVISION or REVAND must be increased to ensure that software can differentiate the different revisions of the component. If REVISION is increased then REVAND should be set to 0.

This field reads as an IMPLEMENTATION DEFINED value.

CMOD, bits [3:0]


Customer Modified.

Indicates the component has been modified.

A value of 0b0000 means the component is not modified from the original design.

Any other value means the component has been modified in an IMPLEMENTATION DEFINED way.

For any two components with the same Unique Component Identifier:

  • If the value of the CMOD fields of both components equals zero, the components are identical.
  • If the CMOD fields of both components have the same non-zero value, it does not necessarily mean that they have the same modifications.
  • If the value of the CMOD field of either of the two components is non-zero, they might not be identical, even though they have the same Unique Component Identifier.

This field reads as an IMPLEMENTATION DEFINED value.

Accessing the TRCPIDR3

External debugger accesses to this register are unaffected by the OS Lock.

TRCPIDR3 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RO.