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TRCSTATR, Trace Status Register
The TRCSTATR characteristics are:
Purpose
Returns the trace unit status.
Configuration
External register TRCSTATR bits [31:0] are architecturally mapped to AArch64 System register TRCSTATR[31:0] .
This register is present only when ETE is implemented. Otherwise, direct accesses to TRCSTATR are RES0.
Attributes
TRCSTATR is a 32-bit register.
Field descriptions
The TRCSTATR bit assignments are:
Bits [31:2]
Reserved, RES0.
PMSTABLE, bit [1]
Programmers' model stable.
PMSTABLE | Meaning |
---|---|
0b0 |
The programmers' model is not stable. |
0b1 |
The programmers' model is stable. |
This bit is UNKNOWN while the trace unit is enabled.
IDLE, bit [0]
Idle status.
IDLE | Meaning |
---|---|
0b0 |
The trace unit is not idle. |
0b1 |
The trace unit is idle. |
Accessing the TRCSTATR
TRCSTATR can be accessed through the external debug interface:
Component | Offset |
---|---|
ETE | 0x00C |
This interface is accessible as follows:
- When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.