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ID_DFR1_EL1, Debug Feature Register 1

The ID_DFR1_EL1 characteristics are:

Purpose

Provides top level information about the debug system in AArch32.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

Configuration

AArch64 System register ID_DFR1_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_DFR1[31:0] .

This register is present only from Armv8.6. Otherwise, direct accesses to ID_DFR1_EL1 are RES0.

Attributes

ID_DFR1_EL1 is a 64-bit register.

Field descriptions

The ID_DFR1_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0MTPMU
313029282726252423222120191817161514131211109876543210

Bits [63:4]

Reserved, RES0.

MTPMU, bits [3:0]

From Armv8.6:

Multi-threaded PMU extension. Defined values are:

MTPMUMeaning
0b0000

ARMv8.6-MTPMU not implemented. If PMUv3 is implemented, it is IMPLEMENTATION DEFINED whether PMEVTYPER<n>_EL0.MT are read/write or RES0.

0b0001

ARMv8.6-MTPMU implemented and PMEVTYPER<n>_EL0.MT are read/write. When ARMv8.6-MTPMU is disabled, the Effective values of PMEVTYPER<n>.MT are 0.

0b1111

ARMv8.6-MTPMU not implemented. If PMUv3 is implemented, PMEVTYPER<n>_EL0.MT are RES0.

All other values are reserved.

ARMv8.6-MTPMU implements the functionality identified by the value 0b0001.

In an Armv8.6-compliant implementation that includes PMUv3, the value 0b0000 is not permitted.

In an implementation that does not include PMUv3, the value 0b0001 is not permitted.


Otherwise:

Reserved, RES0.

Accessing the ID_DFR1_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_DFR1_EL1

op0op1CRnCRmop2
0b110b0000b00000b00110b101
if PSTATE.EL == EL0 then
    if IsFeatureImplemented("ARMv8.4-IDST") then
        if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_DFR1_EL1) || boolean IMPLEMENTATION_DEFINED "ID_DFR1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_DFR1_EL1;
elsif PSTATE.EL == EL2 then
    return ID_DFR1_EL1;
elsif PSTATE.EL == EL3 then
    return ID_DFR1_EL1;
              


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