AMCIDR1, Activity Monitors Component Identification Register 1
The AMCIDR1 characteristics are:
Provides information to identify an activity monitors component.
For more information, see About the Component identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The power domain of AMCIDR1 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCIDR1 are RES0.
AMCIDR1 is a 32-bit register.
The AMCIDR1 bit assignments are:
CLASS, bits [7:4]
Component class. Reads as 0x9, CoreSight component.
PRMBL_1, bits [3:0]
Preamble. Reads as 0x0.
Accessing the AMCIDR1
AMCIDR1 can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO.