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CNTNSAR, Counter-timer Non-secure Access Register

The CNTNSAR characteristics are:


Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses.


The power domain of CNTNSAR is IMPLEMENTATION DEFINED. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a reset of the reset domain in which the register is implemented. The register is not affected by a reset of any other reset domain.

For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.


CNTNSAR is a 32-bit register.

Field descriptions

The CNTNSAR bit assignments are:


Bits [31:8]

Reserved, RES0.

NS<n>, bit [n], for n = 0 to 7

Non-secure access to frame n. The possible values of this bit are:


Secure access only. Behaves as RES0 to Non-secure accesses.


Secure and Non-secure accesses permitted.

This bit also determines whether, in the CNTCTLBase frame, CNTACR<n> and CNTVOFF<n> are accessible to Non-secure accesses.

If frame CNTBase<n>:

  • Is not implemented, then NS<n> is RES0.
  • Is not Configurable access, and is accessible only by Secure accesses, then NS<n> is RES0.
  • Is not Configurable access, and is accessible by both Secure and Non-secure accesses, then NS<n> is RES1.

This field resets to an architecturally UNKNOWN value.

Accessing the CNTNSAR

In a system that recognizes two Security states, this register is only accessible by Secure accesses.

CNTNSAR can be accessed through the memory-mapped interfaces:


Accesses on this interface are RW.

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