CNTSCR, Counter Scale Register
The CNTSCR characteristics are:
Enables the counter, controls the counter frequency setting, and controls counter behavior during debug.
The power domain of CNTSCR is IMPLEMENTATION DEFINED. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a reset of the reset domain in which the register is implemented. The register is not affected by a reset of any other reset domain.
This register is present only when ARMv8.4-CNTSC is implemented. Otherwise, direct accesses to CNTSCR are RES0.
For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
CNTSCR is a 32-bit register.
The CNTSCR bit assignments are:
ScaleVal, bits [31:0]
When counter scaling is enabled, ScaleVal is the amount added to the counter value for every counter tick.
Counter tick is defined as one period of the current operating frequency of the Generic counter.
ScaleVal is expressed as an unsigned fixed point number with an 8-bit integer value and a 24-bit fractional value.
- The counter value becomes UNKNOWN.
- The counter value remains UNKNOWN on future ticks of the clock.
This field resets to an architecturally UNKNOWN value.
Accessing the CNTSCR
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.
CNTSCR can be accessed through the memory-mapped interfaces:
Accesses on this interface are RW.