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ERRPIDR0, Peripheral Identification Register 0

The ERRPIDR0 characteristics are:


Provides discovery information about the component.

For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.


Implementation of this register is OPTIONAL.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRPIDR0 are RES0.


ERRPIDR0 is a 32-bit register.

Field descriptions

The ERRPIDR0 bit assignments are:


Bits [31:8]

Reserved, RES0.

PART_0, bits [7:0]

Part number, bits [7:0].

The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number, and:

  • If a 12-bit part number is used, it is stored in ERRPIDR1.PART_1 and this field.

  • If a 16-bit part number is used, it is stored in ERRPIDR2.PART_2, ERRPIDR1.PART_1 and this field.

This field reads as an IMPLEMENTATION DEFINED value.

Accessing the ERRPIDR0

ERRPIDR0 can be accessed through the memory-mapped interfaces:


Accesses on this interface are RO.