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ERRPIDR1, Peripheral Identification Register 1

The ERRPIDR1 characteristics are:


Provides discovery information about the component.

For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.


Implementation of this register is OPTIONAL.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRPIDR1 are RES0.


ERRPIDR1 is a 32-bit register.

Field descriptions

The ERRPIDR1 bit assignments are:


Bits [31:8]

Reserved, RES0.

DES_0, bits [7:4]

Designer, JEP106 identification code, bits [3:0]. This field and ERRPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component.

The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component.


For a component designed by Arm Limited, the JEP106 identification code is 0x3B.

This field reads as an IMPLEMENTATION DEFINED value.

PART_1, bits [3:0]

Part number, bits [11:8]

The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number, and:

  • If a 12-bit part number is used, it is stored in this field and ERRPIDR0.PART_0.

  • If a 16-bit part number is used, it is stored in ERRPIDR2.PART_2, this field, and ERRPIDR0.PART_0.

This field reads as an IMPLEMENTATION DEFINED value.

Accessing the ERRPIDR1

ERRPIDR1 can be accessed through the memory-mapped interfaces:


Accesses on this interface are RO.

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