GICC_AHPPIR, CPU Interface Aliased Highest Priority Pending Interrupt Register
The GICC_AHPPIR characteristics are:
If the highest priority pending interrupt is in Group 1, this register provides the INTID of the highest priority pending interrupt on the CPU interface.
GICC_AHPPIR is a 32-bit register.
The GICC_AHPPIR bit assignments are:
INTID, bits [23:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
Accessing the GICC_AHPPIR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_HPPIR1 provides equivalent functionality.
- For AArch64 implementations, ICC_HPPIR1_EL1 provides equivalent functionality.
If the highest priority pending interrupt is in Group 0, a read of this register returns the special INTID 1023.
Interrupt identifiers corresponding to an interrupt group that is not enabled are ignored.
If the highest priority pending interrupt is a direct interrupt that is both individually enabled in the Distributor and part of an interrupt group that is enabled in the Distributor, and the interrupt group is disabled in the CPU interface for this PE, this register returns the special INTID 1023.
See Preemption for more information about pending interrupts that are not considered when determining the highest priority pending interrupt.
When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.
GICC_AHPPIR can be accessed through the memory-mapped interfaces:
|GIC CPU interface||0x0028||GICC_AHPPIR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RO.
- When IsAccessSecure() accesses to this register are RO.
- When !IsAccessSecure() accesses to this register are RO.