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MPAMF_IDR, MPAM Features Identification Register

The MPAMF_IDR characteristics are:

Purpose

Indicates which memory partitioning and monitoring features are present on this MSC. MPAMF_IDR_s indicates the MPAM features accessed from the Secure MPAM feature page. MPAMF_IDR_ns indicates the MPAM features accessed from the Non-secure MPAM feature page.

Configuration

The power domain of MPAMF_IDR is IMPLEMENTATION DEFINED.

Attributes

MAMPF_IDR is 64-bit register when ARMv8.6-MPAM is implemented.

Otherwise, MAMPF_IDR is a 32-bit register.

Field descriptions

The MPAMF_IDR bit assignments are:

When ARMv8.6-MPAM is implemented:

Bits [63:60]

Reserved, RES0.

RIS_MAX, bits [59:56]

When MPAMF_IDR.EXT == 1 and MPAMF_IDR.HAS_RIS == 1:

Maximum RIS value supported in MPAMCFG_PART_SEL. Must be 0b0000 if MPAMF_IDR.HAS_RIS == 0.


Otherwise:

Reserved, RES0.

Bits [55:40]

Reserved, RES0.

HAS_ESR, bit [39]

When MPAMF_IDR.EXT == 1:

MPAMF_ESR is implemented.

HAS_ESRMeaning
0b0

MPAMF_ESR, MPAM_ECR and MPAM error handling are not implemented.

0b1

MPAMF_ESR, MPAM_ECR and MPAM error handling are implemented.


Otherwise:

Reserved, RES0.

HAS_EXTD_ESR, bit [38]

When MPAMF_IDR.EXT == 1:

MPAMF_ESR is 64 bits.

HAS_EXTD_ESRMeaning
0b0

MPAMF_ESR is 32 bits.

0b1

MPAMF_ESR is 64 bits.


Otherwise:

Reserved, RES0.

NO_IMPL_MSMON, bit [37]

When MPAMF_IDR.EXT == 1 and MPAMF_IDR.HAS_IMPL_IDR == 1:

MPAMF_IMPL_IDR defines no IMPLEMENTATION DEFINED resource monitors.

NO_IMPL_MSMONMeaning
0b0

MPAMF_IMPL_IDR defines at least one IMPLEMENTATION DEFINED resource monitor.

0b1

MPAMF_IMPL_IDR does not define any IMPLEMENTATION DEFINED resource monitors.


Otherwise:

Reserved, RES0.

NO_IMPL_PART, bit [36]

When MPAMF_IDR.EXT == 1 and MPAMF_IDR.HAS_IMPL_IDR == 1:

MPAMF_IMPL_IDR defines no IMPLEMENTATION DEFINED resource controls.

NO_IMPL_PARTMeaning
0b0

MPAMF_IMPL_IDR defines at least one IMPLEMENTATION DEFINED resource control.

0b1

MPAMF_IMPL_IDR does not define any IMPLEMENTATION DEFINED resource controls.


Otherwise:

Reserved, RES0.

Bits [35:33]

Reserved, RES0.

HAS_RIS, bit [32]

When MPAMF_IDR.EXT == 1:

Has resource instance selector. Indicates that MPAMCFG_PART_SEL contains the RIS field that selects a resource instance to control.

HAS_RISMeaning
0b0

MPAMCFG_PART_SEL does not implement the MPAMFCFG_PART_SEL.RIS field or multiple resource instance suport.

0b1

MPAMCFG_PART_SEL implements the MPAMFCFG_PART_SEL.RIS field and MPAM resource instance numbers up to MPAMF_IDR.RIS_MAX.


Otherwise:

Reserved, RES0.

HAS_PARTID_NRW, bit [31]

Has PARTID narrowing.

HAS_PARTID_NRWMeaning
0b0

Does not have MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID or intPARTID mapping support.

0b1

Supports the MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID registers.

HAS_MSMON, bit [30]

Has resource monitors. Indicates whether this MSC has MPAM resource monitors.

HAS_MSMONMeaning
0b0

Does not support MPAM resource monitoring by groups or MPAMF_MSMON_IDR.

0b1

Supports resource monitoring by matching a combination of PARTID and PMG. See MPAMF_MSMON_IDR.

HAS_IMPL_IDR, bit [29]

Has MPAMF_IMPL_IDR. Indicates whether this MSC has the implementation-specific MPAM features register, MPAMF_IMPL_IDR.

HAS_IMPL_IDRMeaning
0b0

Does not have MPAMF_IMPL_IDR.

0b1

Has MPAMF_IMPL_IDR.

EXT, bit [28]

Extended MPAMF_IDR.

EXTMeaning
0b0

MPAMF_IDR has no defined bits in [63:32]. The register is effectively 32 bits.

0b1

MPAMF_IDR has bits defined in [63:32]. The register is 64-bits.

HAS_PRI_PART, bit [27]

Has priority partitioning. Indicates whether this MSC implements MPAM priority partitioning and MPAMF_PRI_IDR.

HAS_PRI_PARTMeaning
0b0

Does not support priority partitioning or have MPAMF_PRI_IDR.

0b1

Has MPAMF_PRI_IDR.

HAS_MBW_PART, bit [26]

Has memory bandwidth partitioning. Indicates whether this MSC implements MPAM memory bandwidth partitioning and MPAMF_MBW_IDR.

HAS_MBW_PARTMeaning
0b0

Does not support memory bandwidth partitioning or have MPAMF_MBW_IDR register.

0b1

Has MPAMF_MBW_IDR register.

HAS_CPOR_PART, bit [25]

Has cache portion partitioning. Indicates whether this MSC implements MPAM cache portion partitioning and MPAMF_CPOR_IDR.

HAS_CPOR_PARTMeaning
0b0

Does not support cache portion partitioning or have MPAMF_CPOR_IDR or MPAMCFG_CPBM registers.

0b1

Has MPAMF_CPOR_IDR and MPAMCFG_CPBM registers.

HAS_CCAP_PART, bit [24]

Has cache capacity partitioning. Indicates whether this MSC implements MPAM cache capacity partitioning and the MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.

HAS_CCAP_PARTMeaning
0b0

Does not support cache capacity partitioning or have MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.

0b1

Has MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.

PMG_MAX, bits [23:16]

Maximum value of Non-secure PMG supported by this component.

PARTID_MAX, bits [15:0]

Maximum value of Non-secure PARTID supported by this component.

Otherwise:
313029282726252423222120191817161514131211109876543210
HAS_PARTID_NRWHAS_MSMONHAS_IMPL_IDREXTHAS_PRI_PARTHAS_MBW_PARTHAS_CPOR_PARTHAS_CCAP_PARTPMG_MAXPARTID_MAX
313029282726252423222120191817161514131211109876543210

HAS_PARTID_NRW, bit [31]

Has PARTID narrowing.

HAS_PARTID_NRWMeaning
0b0

Does not have MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID or intPARTID mapping support.

0b1

Supports the MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID registers.

HAS_MSMON, bit [30]

Has resource monitors. Indicates whether this MSC has MPAM resource monitors.

HAS_MSMONMeaning
0b0

Does not support MPAM resource monitoring by groups or MPAMF_MSMON_IDR.

0b1

Supports resource monitoring by matching a combination of PARTID and PMG. See MPAMF_MSMON_IDR.

HAS_IMPL_IDR, bit [29]

Has MPAMF_IMPL_IDR. Indicates whether this MSC has the implementation-specific MPAM features register, MPAMF_IMPL_IDR.

HAS_IMPL_IDRMeaning
0b0

Does not have MPAMF_IMPL_IDR.

0b1

Has MPAMF_IMPL_IDR.

EXT, bit [28]

From Armv8.6:

Extended MPAMF_IDR.

EXTMeaning
0b0

MPAMF_IDR has no defined bits in [63:32]. The register is effectively 32 bits.

0b1

MPAMF_IDR has bits defined in [63:32]. The register is 64-bits.


Otherwise:

Reserved, RES0.

HAS_PRI_PART, bit [27]

Has priority partitioning. Indicates whether this MSC implements MPAM priority partitioning and MPAMF_PRI_IDR.

HAS_PRI_PARTMeaning
0b0

Does not support priority partitioning or have MPAMF_PRI_IDR.

0b1

Has MPAMF_PRI_IDR.

HAS_MBW_PART, bit [26]

Has memory bandwidth partitioning. Indicates whether this MSC implements MPAM memory bandwidth partitioning and MPAMF_MBW_IDR.

HAS_MBW_PARTMeaning
0b0

Does not support memory bandwidth partitioning or have MPAMF_MBW_IDR register.

0b1

Has MPAMF_MBW_IDR register.

HAS_CPOR_PART, bit [25]

Has cache portion partitioning. Indicates whether this MSC implements MPAM cache portion partitioning and MPAMF_CPOR_IDR.

HAS_CPOR_PARTMeaning
0b0

Does not support cache portion partitioning or have MPAMF_CPOR_IDR or MPAMCFG_CPBM registers.

0b1

Has MPAMF_CPOR_IDR and MPAMCFG_CPBM registers.

HAS_CCAP_PART, bit [24]

Has cache capacity partitioning. Indicates whether this MSC implements MPAM cache capacity partitioning and the MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.

HAS_CCAP_PARTMeaning
0b0

Does not support cache capacity partitioning or have MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.

0b1

Has MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.

PMG_MAX, bits [23:16]

Maximum value of Non-secure PMG supported by this component.

PARTID_MAX, bits [15:0]

Maximum value of Non-secure PARTID supported by this component.

Accessing the MPAMF_IDR

This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.

MPAMF_IDR is read-only.

MPAMF_IDR must be readable from the Non-secure and Secure MPAM feature pages.

MPAMF_IDR is permitted to have the same contents when read from either the Secure and Non-secure MPAM feature pages unless the register contents is different for Secure and Non-secure versions, when there must be separate registers in the Secure (MPAMF_IDR_s) and Non-secure (MPAMF_IDR_ns) MPAM feature pages.

MPAMF_IDR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x0000MPAMF_IDR_s

Accesses on this interface are RO.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_ns0x0000MPAMF_IDR_ns

Accesses on this interface are RO.



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