TRCDEVARCH, Device Architecture Register
The TRCDEVARCH characteristics are:
Provides discovery information for the component.
For additional information see the CoreSight Architecture Specification.
External register TRCDEVARCH bits [31:0] are architecturally mapped to AArch64 System register TRCDEVARCH[31:0] .
This register is present only when ETE is implemented. Otherwise, direct accesses to TRCDEVARCH are RES0.
TRCDEVARCH is a 32-bit register.
The TRCDEVARCH bit assignments are:
ARCHITECT, bits [31:21]
Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
JEP106 continuation code 0x4, ID code 0x3B. Arm Limited.
Other values are defined by the JEDEC JEP106 standard.
This field reads as 0x23B.
PRESENT, bit 
DEVARCH Present. Defines that the DEVARCH register is present.
Device Architecture information not present.
Device Architecture information present.
This bit reads as 0b1.
REVISION, bits [19:16]
Revision. Defines the architecture revision of the component.
ETE Version 1.0.
All other values are reserved.
ARCHVER, bits [15:12]
Architecture Version. Defines the architecture version of the component.
ETE Version 1.
ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHVER is ARCHID[15:12].
This field reads as 0x5.
ARCHPART, bits [11:0]
Architecture Part. Defines the architecture of the component.
Arm PE trace architecture.
ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHPART is ARCHID[11:0].
This field reads as 0xA13.
Accessing the TRCDEVARCH
External debugger accesses to this register are unaffected by the OS Lock.
TRCDEVARCH can be accessed through the external debug interface:
This interface is accessible as follows:
- When !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.