TRCEXTINSELR<n>, External Input Select Register <n>, n = 0 - 3
The TRCEXTINSELR<n> characteristics are:
Use this to set, or read, which External Inputs are resources to the trace unit.
External register TRCEXTINSELR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCEXTINSELR<n>[31:0] .
RW fields in this register reset to architecturally UNKNOWN values.
This register is present only when ETE is implemented and TRCIDR5.NUMEXTINSEL > n. Otherwise, direct accesses to TRCEXTINSELR<n> are RES0.
TRCEXTINSELR<n> is a 32-bit register.
The TRCEXTINSELR<n> bit assignments are:
evtCount, bits [15:0]
PMU event to select.
The event number as defined by the Arm ARM.
Software must program this field with a PMU event that is supported by the PE being programmed.
There are three ranges of PMU event numbers:
- PMU event numbers in the range 0x0000 to 0x003F are common architectural and microarchitectural events.
- PMU event numbers in the range 0x0040 to 0x00BF are Arm recommended common architectural and microarchitectural PMU events.
- PMU event numbers in the range 0x00C0 to 0x03FF are IMPLEMENTATION DEFINED PMU events.
If evtCount is programmed to a PMU event that is reserved or not supported by the PE, the behavior depends on the PMU event type:
- For the range 0x0000 to 0x003F, then the PMU event is not active, and the value returned by a direct or external read of the evtCount field is the value written to the field.
- For IMPLEMENTATION DEFINED PMU events, it is UNPREDICTABLE what PMU event, if any, is counted, and the value returned by a direct or external read of the evtCount field is UNKNOWN.
UNPREDICTABLE means the PMU event must not expose privileged information.
Arm recommends that the behavior across a family of implementations is defined such that if a given implementation does not include a PMU event from a set of common IMPLEMENTATION DEFINED PMU events, then no PMU event is counted and the value read back on evtCount is the value written.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Accessing the TRCEXTINSELR<n>
Must be programmed if any of the following is true: TRCRSCTLR<a>.GROUP == 0b0000 and TRCRSCTLR<a>.EXTIN[n] == 0b1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
TRCEXTINSELR<n> can be accessed through the external debug interface:
|ETE||0x120 + 4n|
This interface is accessible as follows:
- When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RW.