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TRCPIDR1, Peripheral Identification Register 1

The TRCPIDR1 characteristics are:


Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.


This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR1 are RES0.

There are no configuration notes.


TRCPIDR1 is a 32-bit register.

Field descriptions

The TRCPIDR1 bit assignments are:


Bits [31:8]

Reserved, RES0.

DES_0, bits [7:4]


Designer, JEP106 identification code, bits [3:0]. TRCPIDR1.DES_0 and TRCPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC

Note that for a component designed by Arm Limited, the JEP106 identification code is 0x3B.

This field reads as an IMPLEMENTATION DEFINED value.

PART_1, bits [3:0]


Part number, bits [11:8].

This field reads as an IMPLEMENTATION DEFINED value.

Accessing the TRCPIDR1

External debugger accesses to this register are unaffected by the OS Lock.

TRCPIDR1 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RO.