You copied the Doc URL to your clipboard.
AIDR, Auxiliary ID Register
The AIDR characteristics are:
Purpose
Provides IMPLEMENTATION DEFINED identification information.
The value of this register must be used in conjunction with the value of MIDR.
Configuration
AArch32 System register AIDR bits [31:0] are architecturally mapped to AArch64 System register AIDR_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to AIDR are UNKNOWN.
Attributes
AIDR is a 32-bit register.
Field descriptions
The AIDR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED, bits [31:0]
IMPLEMENTATION DEFINED.
Accessing the AIDR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b001 | 0b0000 | 0b0000 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID1 == '1' then
AArch32.TakeHypTrapException(0x03);
else
return AIDR;
elsif PSTATE.EL == EL2 then
return AIDR;
elsif PSTATE.EL == EL3 then
return AIDR;