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HDFGWTR_EL2, Hypervisor Debug Fine-Grained Write Trap Register

The HDFGWTR_EL2 characteristics are:

Purpose

Provides controls for traps of MSR and MCR writes of debug, trace, PMU, and Statistical Profiling System registers.

Configuration

This register is present only when ARMv8.6-FGT is implemented. Otherwise, direct accesses to HDFGWTR_EL2 are UNDEFINED.

Attributes

HDFGWTR_EL2 is a 64-bit register.

Field descriptions

The HDFGWTR_EL2 bit assignments are:

Bits [63:58]

Reserved, RES0.

PMUSERENR_EL0, bit [57]

When PMUv3 is implemented:

Trap MSR writes of PMUSERENR_EL0 at EL1 using AArch64 to EL2.

PMUSERENR_EL0Meaning
0b0

MSR writes of PMUSERENR_EL0 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMUSERENR_EL0 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRBTRG_EL1, bit [56]

When TRBE is implemented:

Trap MSR writes of TRBTRG_EL1 at EL1 using AArch64 to EL2.

TRBTRG_EL1Meaning
0b0

MSR writes of TRBTRG_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRBTRG_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRBSR_EL1, bit [55]

When TRBE is implemented:

Trap MSR writes of TRBSR_EL1 at EL1 using AArch64 to EL2.

TRBSR_EL1Meaning
0b0

MSR writes of TRBSR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRBSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRBPTR_EL1, bit [54]

When TRBE is implemented:

Trap MSR writes of TRBPTR_EL1 at EL1 using AArch64 to EL2.

TRBPTR_EL1Meaning
0b0

MSR writes of TRBPTR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRBPTR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRBMAR_EL1, bit [53]

When TRBE is implemented:

Trap MSR writes of TRBMAR_EL1 at EL1 using AArch64 to EL2.

TRBMAR_EL1Meaning
0b0

MSR writes of TRBMAR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRBMAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRBLIMITR_EL1, bit [52]

When TRBE is implemented:

Trap MSR writes of TRBLIMITR_EL1 at EL1 using AArch64 to EL2.

TRBLIMITR_EL1Meaning
0b0

MSR writes of TRBLIMITR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRBLIMITR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

Bit [51]

Reserved, RES0.

TRBBASER_EL1, bit [50]

When TRBE is implemented:

Trap MSR writes of TRBBASER_EL1 at EL1 using AArch64 to EL2.

TRBBASER_EL1Meaning
0b0

MSR writes of TRBBASER_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRBBASER_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRFCR_EL1, bit [49]

When ARMv8.4-Trace is implemented:

Trap MSR writes of TRFCR_EL1 at EL1 using AArch64 to EL2.

TRFCR_EL1Meaning
0b0

MSR writes of TRFCR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRFCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRCVICTLR, bit [48]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of TRCVICTLR at EL1 using AArch64 to EL2.

TRCVICTLRMeaning
0b0

MSR writes of TRCVICTLR are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCVICTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

Bit [47]

Reserved, RES0.

TRCSSCSRn, bit [46]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of TRCSSCSR<n> at EL1 using AArch64 to EL2.

TRCSSCSRnMeaning
0b0

MSR writes of TRCSSCSR<n> are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCSSCSR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

If Single-shot Comparator n is not implementented, a write of TRCSSCSR<n> is UNDEFINED.

This bit is RES0 if TRCSSCSR<n> are not implemented.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRCSEQSTR, bit [45]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of TRCSEQSTR at EL1 using AArch64 to EL2.

TRCSEQSTRMeaning
0b0

MSR writes of TRCSEQSTR are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCSEQSTR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

This bit is RES0 if TRCSEQSTR is not implemented.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRCPRGCTLR, bit [44]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of TRCPRGCTLR at EL1 using AArch64 to EL2.

TRCPRGCTLRMeaning
0b0

MSR writes of TRCPRGCTLR are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCPRGCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

Bit [43]

Reserved, RES0.

TRCOSLAR, bit [42]

When the Trace Extension is implemented, System register access to the PE Trace Unit registers is implemented and ETMv4 is implemented:

Trap MSR writes of TRCOSLAR at EL1 using AArch64 to EL2.

TRCOSLARMeaning
0b0

MSR writes of TRCOSLAR are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCOSLAR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRCIMSPECn, bit [41]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of TRCIMSPEC<n> at EL1 using AArch64 to EL2.

TRCIMSPECnMeaning
0b0

MSR writes of TRCIMSPEC<n> are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCIMSPEC<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

TRCIMSPEC<1-7> are optional. If TRCIMSPEC<n> is not implemented, a write of TRCIMSPEC<n> is UNDEFINED.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

Bits [40:38]

Reserved, RES0.

TRCCNTVRn, bit [37]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of TRCCNTVR<n> at EL1 using AArch64 to EL2.

TRCCNTVRnMeaning
0b0

MSR writes of TRCCNTVR<n> are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCCNTVR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

If Counter n is not implemented, a write of TRCCNTVR<n> is UNDEFINED.

This bit is RES0 if TRCCNTVR<n> are not implemented.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRCCLAIM, bit [36]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

TRCCLAIMMeaning
0b0

MSR writes of the System registers listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TRCAUXCTLR, bit [35]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of TRCAUXCTLR at EL1 using AArch64 to EL2.

TRCAUXCTLRMeaning
0b0

MSR writes of TRCAUXCTLR are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of TRCAUXCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

Bit [34]

Reserved, RES0.

TRC, bit [33]

When the Trace Extension is implemented and System register access to the PE Trace Unit registers is implemented:

Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

  • TRCACATR<n>.
  • TRCACVR<n>.
  • TRCBBCTLR.
  • TRCCCCTLR.
  • TRCCIDCCTLR<n>.
  • TRCCIDCVR<n>.
  • TRCCNTCTLR<n>.
  • TRCCNTRLDVR<n>.
  • TRCCONFIGR.
  • TRCEVENTCTL0R.
  • TRCEVENTCTL1R.
  • TRCEXTINSELR<n>, if ETE is implemented.
  • TRCEXTINSELR, if ETMv4 is implemented.
  • TRCRSCTLR<n>.
  • TRCRSR, if ETE is implemented.
  • TRCSEQEVR<n>.
  • TRCSEQRSTEVR.
  • TRCSSCCR<n>.
  • TRCSSPCICR<n>.
  • TRCSTALLCTLR.
  • TRCSYNCPR.
  • TRCTRACEIDR.
  • TRCTSCTLR.
  • TRCVIIECTLR.
  • TRCVIPCSSCTLR.
  • TRCVISSCTLR.
  • TRCVMIDCCTLR<n>.
  • TRCVMIDCVR<n>.
TRCMeaning
0b0

MSR writes of the System registers listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

A write of an unimplemented register is UNDEFINED.

TRCEXTINSELR<n> and TRCRSR are only implemented if ETE is implemented.

TRCEXTINSELR is only implemented if ETE is not implemented and ETMv4 is implemented.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMSLATFR_EL1, bit [32]

When SPE is implemented:

Trap MSR writes of PMSLATFR_EL1 at EL1 using AArch64 to EL2.

PMSLATFR_EL1Meaning
0b0

MSR writes of PMSLATFR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMSLATFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMSIRR_EL1, bit [31]

When SPE is implemented:

Trap MSR writes of PMSIRR_EL1 at EL1 using AArch64 to EL2.

PMSIRR_EL1Meaning
0b0

MSR writes of PMSIRR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMSIRR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

Bit [30]

Reserved, RES0.

PMSICR_EL1, bit [29]

When SPE is implemented:

Trap MSR writes of PMSICR_EL1 at EL1 using AArch64 to EL2.

PMSICR_EL1Meaning
0b0

MSR writes of PMSICR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMSICR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMSFCR_EL1, bit [28]

When SPE is implemented:

Trap MSR writes of PMSFCR_EL1 at EL1 using AArch64 to EL2.

PMSFCR_EL1Meaning
0b0

MSR writes of PMSFCR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMSFCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMSEVFR_EL1, bit [27]

When SPE is implemented:

Trap MSR writes of PMSEVFR_EL1 at EL1 using AArch64 to EL2.

PMSEVFR_EL1Meaning
0b0

MSR writes of PMSEVFR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMSEVFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMSCR_EL1, bit [26]

When SPE is implemented:

Trap MSR writes of PMSCR_EL1 at EL1 using AArch64 to EL2.

PMSCR_EL1Meaning
0b0

MSR writes of PMSCR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMBSR_EL1, bit [25]

When SPE is implemented:

Trap MSR writes of PMBSR_EL1 at EL1 using AArch64 to EL2.

PMBSR_EL1Meaning
0b0

MSR writes of PMBSR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMBSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMBPTR_EL1, bit [24]

When SPE is implemented:

Trap MSR writes of PMBPTR_EL1 at EL1 using AArch64 to EL2.

PMBPTR_EL1Meaning
0b0

MSR writes of PMBPTR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMBPTR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMBLIMITR_EL1, bit [23]

When SPE is implemented:

Trap MSR writes of PMBLIMITR_EL1 at EL1 using AArch64 to EL2.

PMBLIMITR_EL1Meaning
0b0

MSR writes of PMBLIMITR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of PMBLIMITR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

Bit [22]

Reserved, RES0.

PMCR_EL0, bit [21]

When PMUv3 is implemented:

Trap MSR writes of PMCR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCR at EL0 using AArch32 when EL1 is using AArch64 to EL2.

PMCR_EL0Meaning
0b0

MSR writes of PMCR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCR at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes of PMCR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes of PMCR at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMSWINC_EL0, bit [20]

When PMUv3 is implemented:

Trap MSR writes of PMSWINC_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSWINC at EL0 using AArch32 when EL1 is using AArch64 to EL2.

PMSWINC_EL0Meaning
0b0

MSR writes of PMSWINC_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSWINC at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes of PMSWINC_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes of PMSWINC at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMSELR_EL0, bit [19]

When PMUv3 is implemented:

Trap MSR writes of PMSELR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSELR at EL0 using AArch32 when EL1 is using AArch64 to EL2.

PMSELR_EL0Meaning
0b0

MSR writes of PMSELR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSELR at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes of PMSELR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes of PMSELR at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMOVS, bit [18]

When PMUv3 is implemented:

Trap MSR writes and MCR writes of multiple System registers.

Enables a trap to EL2 the following operations:

PMOVSMeaning
0b0

The operations listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes at EL1 and EL0 using AArch64 of PMOVSCLR_EL0 and PMOVSSET_EL0 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes at EL0 using AArch32 of PMOVSR and PMOVSSET are trapped to EL2 and reported with EC syndrome value 0x03, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMINTEN, bit [17]

When PMUv3 is implemented:

Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

PMINTENMeaning
0b0

MSR writes of the System registers listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMCNTEN, bit [16]

When PMUv3 is implemented:

Trap MSR writes and MCR writes of multiple System registers.

Enables a trap to EL2 the following operations:

PMCNTENMeaning
0b0

The operations listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes at EL1 and EL0 using AArch64 of PMCNTENCLR_EL0 and PMCNTENSET_EL0 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes at EL0 using AArch32 of PMCNTENCLR and PMCNTENSET are trapped to EL2 and reported with EC syndrome value 0x03, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMCCNTR_EL0, bit [15]

When PMUv3 is implemented:

Trap MSR writes of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MCR and MCRR writes of PMCCNTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.

PMCCNTR_EL0Meaning
0b0

MSR writes of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MCR and MCRR writes of PMCCNTR at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes of PMCCNTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR and MCRR writes of PMCCNTR at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03 (for MCR) or 0x04 (for MCRR).

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMCCFILTR_EL0, bit [14]

When PMUv3 is implemented:

Trap MSR writes of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCCFILTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.

PMCCFILTR_EL0Meaning
0b0

MSR writes of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCCFILTR at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes of PMCCFILTR at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

PMCCFILTR_EL0 can also be accessed in AArch64 state using PMXEVTYPER_EL0 when PMSELR_EL0.SEL == 31, and PMCCFILTR can also be accessed in AArch32 state using PMXEVTYPER when PMSELR.SEL == 31.

Setting this bit to 1 has no effect on accesses to PMXEVTYPER_EL0 and PMXEVTYPER, regardless of the value of PMSELR_EL0.SEL or PMSELR.SEL.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMEVTYPERn_EL0, bit [13]

When PMUv3 is implemented:

Trap MSR writes and MCR writes of multiple System registers.

Enables a trap to EL2 the following operations:

PMEVTYPERn_EL0Meaning
0b0

The operations listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes at EL1 and EL0 using AArch64 of PMEVTYPER<n>_EL0 and PMXEVTYPER_EL0 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes at EL0 using AArch32 of PMEVTYPER<n> and PMXEVTYPER are trapped to EL2 and reported with EC syndrome value 0x03, unless the write generates a higher priority exception.

When ARMv8.6-FGT is implemented, then, regardless of the value of this bit, for each value n:

  • If event counter n is not implemented, the following accesses are UNDEFINED:

  • If event counter n is implemented and EL2 is implemented and enabled in the current Security state, the following generate a Trap exception to EL2 from EL0 or EL1:

See also HDFGWTR_EL2.PMCCFILTR_EL0.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

PMEVCNTRn_EL0, bit [12]

When PMUv3 is implemented:

Trap MSR writes and MCR writes of multiple System registers.

Enables a trap to EL2 the following operations:

PMEVCNTRn_EL0Meaning
0b0

The operations listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:

  • MSR writes at EL1 and EL0 using AArch64 of PMEVCNTR<n>_EL0 and PMXEVCNTR_EL0 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MCR writes at EL0 using AArch32 of PMEVCNTR<n> and PMXEVCNTR are trapped to EL2 and reported with EC syndrome value 0x03, unless the write generates a higher priority exception.

When ARMv8.6-FGT is implemented, then, regardless of the value of this bit, for each value n:

  • If event counter n is not implemented, the following accesses are UNDEFINED:

  • If event counter n is implemented, and EL2 is implemented and enabled in the current Security state, the following generate a Trap exception to EL2 from EL0 or EL1:

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

OSDLR_EL1, bit [11]

When ARMv8.0-DoubleLock is implemented:

Trap MSR writes of OSDLR_EL1 at EL1 using AArch64 to EL2.

OSDLR_EL1Meaning
0b0

MSR writes of OSDLR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of OSDLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

OSECCR_EL1, bit [10]

Trap MSR writes of OSECCR_EL1 at EL1 using AArch64 to EL2.

OSECCR_EL1Meaning
0b0

MSR writes of OSECCR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of OSECCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

Bit [9]

Reserved, RES0.

OSLAR_EL1, bit [8]

Trap MSR writes of OSLAR_EL1 at EL1 using AArch64 to EL2.

OSLAR_EL1Meaning
0b0

MSR writes of OSLAR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of OSLAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DBGPRCR_EL1, bit [7]

Trap MSR writes of DBGPRCR_EL1 at EL1 using AArch64 to EL2.

DBGPRCR_EL1Meaning
0b0

MSR writes of DBGPRCR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of DBGPRCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

Bit [6]

Reserved, RES0.

DBGCLAIM, bit [5]

Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

DBGCLAIMMeaning
0b0

MSR writes of the System registers listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

MDSCR_EL1, bit [4]

Trap MSR writes of MDSCR_EL1 at EL1 using AArch64 to EL2.

MDSCR_EL1Meaning
0b0

MSR writes of MDSCR_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of MDSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DBGWVRn_EL1, bit [3]

Trap MSR writes of DBGWVR<n>_EL1 at EL1 using AArch64 to EL2.

DBGWVRn_EL1Meaning
0b0

MSR writes of DBGWVR<n>_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of DBGWVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

If watchpoint n is not implemented, a write of DBGWVR<n>_EL1 is UNDEFINED.

In a system where the PE resets into EL2, this field resets to 0.

DBGWCRn_EL1, bit [2]

Trap MSR writes of DBGWCR<n>_EL1 at EL1 using AArch64 to EL2.

DBGWCRn_EL1Meaning
0b0

MSR writes of DBGWCR<n>_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of DBGWCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

If watchpoint n is not implemented, a write of DBGWCR<n>_EL1 is UNDEFINED.

In a system where the PE resets into EL2, this field resets to 0.

DBGBVRn_EL1, bit [1]

Trap MSR writes of DBGBVR<n>_EL1 at EL1 using AArch64 to EL2.

DBGBVRn_EL1Meaning
0b0

MSR writes of DBGBVR<n>_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of DBGBVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

If breakpoint n is not implemented, a write of DBGBVR<n>_EL1 is UNDEFINED.

In a system where the PE resets into EL2, this field resets to 0.

DBGBCRn_EL1, bit [0]

Trap MSR writes of DBGBCR<n>_EL1 at EL1 using AArch64 to EL2.

DBGBCRn_EL1Meaning
0b0

MSR writes of DBGBCR<n>_EL1 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MSR writes of DBGBCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

If breakpoint n is not implemented, a write of DBGBCR<n>_EL1 is UNDEFINED.

In a system where the PE resets into EL2, this field resets to 0.

Accessing the HDFGWTR_EL2

Accesses to this register use the following encodings:

MRS <Xt>, HDFGWTR_EL2

op0op1CRnCRmop2
0b110b1000b00110b00010b101
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
        return NVMem[0x1D8];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return HDFGWTR_EL2;
elsif PSTATE.EL == EL3 then
    return HDFGWTR_EL2;
              

MSR HDFGWTR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00110b00010b101
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
        NVMem[0x1D8] = X[t];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        HDFGWTR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
    HDFGWTR_EL2 = X[t];