ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5
The ID_ISAR5_EL1 characteristics are:
Purpose
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, and ID_ISAR4_EL1.
For general information about the interpretation of the ID registers see Principles of the ID scheme for fields in ID registers.
Configuration
AArch64 System register ID_ISAR5_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR5[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ID_ISAR5_EL1 are UNKNOWN.
Attributes
ID_ISAR5_EL1 is a 64-bit register.
Field descriptions
The ID_ISAR5_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
VCMA | RDM | RES0 | CRC32 | SHA2 | SHA1 | AES | SEVL | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
VCMA, bits [31:28]
Indicates AArch32 support for complex number addition and multiplication where numbers are stored in vectors. Defined values are:
VCMA | Meaning |
---|---|
0b0000 |
The VCMLA and VCADD instructions are not implemented in AArch32. |
0b0001 |
The VCMLA and VCADD instructions are implemented in AArch32. |
All other values are reserved.
ARMv8.3-CompNum implements the functionality identified by 0b0001.
In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.
From Armv8.3, the only permitted value is 0b0001.
RDM, bits [27:24]
Indicates whether the VQRDMLAH and VQRDMLSH instructions are implemented in AArch32 state. Defined values are:
RDM | Meaning |
---|---|
0b0000 |
No VQRDMLAH and VQRDMLSH instructions implemented. |
0b0001 |
VQRDMLAH and VQRDMLSH instructions implemented. |
All other values are reserved.
ARMv8.1-RDMA implements the functionality identified by the value 0b0001.
In Armv8.0, the only permitted value is 0b0000.
From Armv8.1, the only permitted value is 0b0001.
Bits [23:20]
Reserved, RES0.
CRC32, bits [19:16]
Indicates whether the CRC32 instructions are implemented in AArch32 state.
CRC32 | Meaning |
---|---|
0b0000 |
No CRC32 instructions implemented. |
0b0001 |
CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW instructions implemented. |
All other values are reserved.
In Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.1, the only permitted value is 0b0001.
SHA2, bits [15:12]
Indicates whether the SHA2 instructions are implemented in AArch32 state.
SHA2 | Meaning |
---|---|
0b0000 |
No SHA2 instructions implemented. |
0b0001 |
SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 implemented. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
SHA1, bits [11:8]
Indicates whether the SHA1 instructions are implemented in AArch32 state.
SHA1 | Meaning |
---|---|
0b0000 |
No SHA1 instructions implemented. |
0b0001 |
SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 implemented. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
AES, bits [7:4]
Indicates whether the AES instructions are implemented in AArch32 state.
AES | Meaning |
---|---|
0b0000 |
No AES instructions implemented. |
0b0001 |
AESE, AESD, AESMC, and AESIMC implemented. |
0b0010 |
As for 0b0001, plus VMULL (polynomial) instructions operating on 64-bit data quantities. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0010.
SEVL, bits [3:0]
Indicates whether the SEVL instruction is implemented in AArch32 state.
SEVL | Meaning |
---|---|
0b0000 |
SEVL is implemented as a NOP. |
0b0001 |
SEVL is implemented as Send Event Local. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Accessing the ID_ISAR5_EL1
Accesses to this register use the following encodings:
MRS <Xt>, ID_ISAR5_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0010 | 0b101 |
if PSTATE.EL == EL0 then if IsFeatureImplemented("ARMv8.4-IDST") then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_ISAR5_EL1; elsif PSTATE.EL == EL2 then return ID_ISAR5_EL1; elsif PSTATE.EL == EL3 then return ID_ISAR5_EL1;