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EDCIDR1, External Debug Component Identification Register 1

The EDCIDR1 characteristics are:


Provides information to identify an external debug component.

For more information see 'About the Component identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).


Implementation of this register is OPTIONAL.

If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.


EDCIDR1 is a 32-bit register.

Field descriptions

The EDCIDR1 bit assignments are:


Bits [31:8]

Reserved, RES0.

CLASS, bits [7:4]

Component class. Debug component.

Reads as 0b1001.

PRMBL_1, bits [3:0]


Reads as 0b0000.

Accessing the EDCIDR1

EDCIDR1 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When ARMv8.3-DoPD is not implemented or IsCorePowered() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.