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ERRDEVARCH, Device Architecture Register

The ERRDEVARCH characteristics are:

Purpose

Provides discovery information for the component.

Configuration

There are no configuration notes.

Attributes

ERRDEVARCH is a 32-bit register.

Field descriptions

The ERRDEVARCH bit assignments are:

313029282726252423222120191817161514131211109876543210
ARCHITECTPRESENTREVISIONARCHVERARCHPART

ARCHITECT, bits [31:21]

Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.

ARCHITECTMeaning
0b01000111011

JEP106 continuation code 0x4, ID code 0x3B. Arm Limited.

Other values are defined by the JEDEC JEP106 standard.

This field reads as 0x23B.

PRESENT, bit [20]

DEVARCH Present. Defines that the DEVARCH register is present.

PRESENTMeaning
0b0

Device Architecture information not present.

0b1

Device Architecture information present.

This bit reads as 0b1.

REVISION, bits [19:16]

Revision. Defines the architecture revision of the component.

REVISIONMeaning
0b0000

RAS System Architecture v1.0.

0b0001

RAS System Architecture v1.1. As 0b0000 and also:

  • Simplifies ERR<n>STATUS.
  • Adds support for additional ERR<n>MISC<m> registers.
  • Adds support for the optional RAS Timestamp Extension.
  • Adds support for the optional RAS Common Fault Injection Model Extension.

All other values are reserved.

ARCHVER, bits [15:12]

Architecture Version. Defines the architecture version of the component.

ARCHVERMeaning
0b0000

RAS System Architecture v1.

All other values are reserved.

ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHVER is ARCHID[15:12].

This field reads as 0b0000.

ARCHPART, bits [11:0]

Architecture Part. Defines the architecture of the component.

ARCHPARTMeaning
0xA00

RAS System Architecture.

ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHPART is ARCHID[11:0].

This field reads as 0xA00.

Accessing the ERRDEVARCH

ERRDEVARCH can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xFBC

Accesses on this interface are RO.