GICC_APR<n>, CPU Interface Active Priorities Registers, n = 0 - 3
The GICC_APR<n> characteristics are:
Provides information about interrupt active priorities.
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
When GICD_CTLR.DS == 0, these registers are Banked, and Non-secure accesses do not affect Secure operation. The Secure copies of these registers hold active priorities for Group 0 interrupts, and the Non-secure copies provide a Non-secure view of the active priorities for Group 1 interrupts.
GICC_APR1 is only implemented in implementations that support 6 or more bits of priority. GICC_APR2 and GICC_APR3 are only implemented in implementations that support 7 bits of priority.
GICC_APR<n> is a 32-bit register.
The GICC_APR<n> bit assignments are:
IMPLEMENTATION DEFINED, bits [31:0]
This field resets to 0.
Accessing the GICC_APR<n>
These registers are used only when System register access is not enabled. When System register access is enabled the following registers provide equivalent functionality:
- In AArch64:
- In AArch32:
GICC_APR<n> can be accessed through the memory-mapped interfaces:
|GIC CPU interface||0x00D0 + 4n||GICC_APR<n>|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RW.
- When IsAccessSecure() accesses to this register are RW.
- When !IsAccessSecure() accesses to this register are RW.