MIDR_EL1, Main ID Register
The MIDR_EL1 characteristics are:
Provides identification information for the PE, including an implementer code for the device and a device ID number.
External register MIDR_EL1 bits [31:0] are architecturally mapped to AArch64 System register MIDR_EL1[31:0] .
External register MIDR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MIDR[31:0] .
It is IMPLEMENTATION DEFINED whether MIDR_EL1 is implemented in the Core power domain or in the Debug power domain.
MIDR_EL1 is a 32-bit register.
The MIDR_EL1 bit assignments are:
Implementer, bits [31:24]
The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:
|0x00||Reserved for software use|
|0x44||Digital Equipment Corporation|
|0x49||Infineon Technologies AG|
|0x4D||Motorola or Freescale Semiconductor Inc.|
|0x50||Applied Micro Circuits Corporation|
|0x56||Marvell International Ltd.|
Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.
Variant, bits [23:20]
An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.
Architecture, bits [19:16]
The permitted values of this field are:
Architectural features are individually identified in the ID_* registers, see ID registers in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile
All other values are reserved.
PartNum, bits [15:4]
An IMPLEMENTATION DEFINED primary part number for the device.
On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.
Revision, bits [3:0]
An IMPLEMENTATION DEFINED revision number for the device.
Accessing the MIDR_EL1
MIDR_EL1 can be accessed through the external debug interface:
This interface is accessible as follows:
- When IsCorePowered() and !DoubleLockStatus() accesses to this register are RO.
- Otherwise accesses to this register are IMPDEF.