PMPIDR0, Performance Monitors Peripheral Identification Register 0
The PMPIDR0 characteristics are:
Provides information to identify a Performance Monitor component.
For more information see 'About the Peripheral identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).
Implementation of this register is OPTIONAL.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMPIDR0 is a 32-bit register.
The PMPIDR0 bit assignments are:
PART_0, bits [7:0]
Part number, least significant byte.
Accessing the PMPIDR0
PMPIDR0 can be accessed through the external debug interface:
This interface is accessible as follows:
- When ARMv8.3-DoPD is not implemented or IsCorePowered() accesses to this register are RO.
- Otherwise accesses to this register generate an error response.