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TRCTSCTLR, Timestamp Control Register

The TRCTSCTLR characteristics are:


Controls the insertion of global timestamps in the trace stream.


External register TRCTSCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCTSCTLR[31:0] .

This register is present only when ETE is implemented and TRCIDR0.TSSIZE != 0b00000. Otherwise, direct accesses to TRCTSCTLR are RES0.


TRCTSCTLR is a 32-bit register.

Field descriptions

The TRCTSCTLR bit assignments are:


Bits [31:8]

Reserved, RES0.

EVENT_TYPE, bit [7]

When TRCIDR4.NUMRSPAIR != 0b0000:

Chooses the type of Resource Selector.


A single Resource Selector.

TRCTSCTLR.EVENT.SEL[4:0] selects the single Resource Selector, from 0-31, used to activate the resource event.


A Boolean-combined pair of Resource Selectors.

TRCTSCTLR.EVENT.SEL[3:0] selects the Resource Selector pair, from 0-15, that has a Boolean function that is applied to it whose output is used to activate the resource event. TRCTSCTLR.EVENT.SEL[4] is RES0.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Reserved, RES0.

Bits [6:5]

Reserved, RES0.

EVENT_SEL, bits [4:0]

When TRCIDR4.NUMRSPAIR != 0b0000:

Defines the selected Resource Selector or pair of Resource Selectors. TRCTSCTLR.EVENT.TYPE controls whether TRCTSCTLR.EVENT.SEL is the index of a single Resource Selector, or the index of a pair of Resource Selectors.

If an unimplemented Resource Selector is selected using this field, the behavior of the resource event is UNPREDICTABLE, and the resource event might fire or might not fire.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Reserved, RES0.

Accessing the TRCTSCTLR

Must be programmed if TRCCONFIGR.TS == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCTSCTLR can be accessed through the external debug interface:


This interface is accessible as follows:

  • When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RW.