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TLBI ALLE1, TLB Invalidate All, EL1

The TLBI ALLE1 characteristics are:


Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

  • The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.

  • If SCR_EL3.NS is 0 and the entry would be required to translate an address using the Secure EL1&0 translation regime.

  • If SCR_EL3.NS is 1 and the entry would be required to translate an address using the Non-secure EL1&0 translation regime.

The invalidation applies to entries with any VMID.

The invalidation only applies to the PE that executes this System instruction.


For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.


There are no configuration notes.


TLBI ALLE1 is a 64-bit System instruction.

Field descriptions

This instruction has no applicable fields.

The value in the register specified by <Xt> is ignored.

Executing the TLBI ALLE1 instruction

When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:

  • The instruction is UNDEFINED.

  • The instruction behaves as if the Xt field is set to 0b11111.

Accesses to this instruction use the following encodings:

TLBI ALLE1{, <Xt>}

if PSTATE.EL == EL0 then
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
elsif PSTATE.EL == EL2 then
elsif PSTATE.EL == EL3 then