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ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6

The ID_ISAR6_EL1 characteristics are:

Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1 and ID_ISAR5_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.

Configuration

AArch64 System register ID_ISAR6_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR6[31:0] .

This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ID_ISAR6_EL1 are UNKNOWN.

Note

Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Attributes

ID_ISAR6_EL1 is a 64-bit register.

Field descriptions

The ID_ISAR6_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0I8MMBF16SPECRESSBFHMDPJSCVT
313029282726252423222120191817161514131211109876543210

Bits [63:28]

Reserved, RES0.

I8MM, bits [27:24]

Indicates support for Advanced SIMD and floating-point Int8 matrix multiplication instructions in AArch32 state. Defined values of this field are:

I8MMMeaning
0b0000

Int8 matrix multiplication instructions are not implemented.

0b0001

VSMMLA, VSUDOT, VUMMLA, VUSMMLA, and VUSDOT instructions are implemented.

All other values are reserved.

ARMv8.2-AA32I8MM implements the functionality identified by 0b0001.

BF16, bits [23:20]

Indicates support for Advanced SIMD and floating-point BFloat16 instructions in AArch32 state. Defined values are:

BF16Meaning
0b0000

BFloat16 instructions are not implemented.

0b0001

VCVT, VCVTB, VCVTT, VDOT, VFMAL, and VMMLA instructions with BF16 operand or result types are implemented.

All other values are reserved.

ARMv8.2-AA32BF16 implements the functionality identified by 0b0001.

SPECRES, bits [19:16]

Indicates support for Speculation invalidation instructions in AArch32 state. Defined values are:

SPECRESMeaning
0b0000

Prediction invalidation instructions are not implemented.

0b0001

CFPRCTX, DVPRCTX, and CPPRCTX instructions are implemented.

All other values are reserved.

ARMv8.0-PredInv implements the functionality identified by 0b0001.

From Armv8.5, the only permitted value is 0b0001.

SB, bits [15:12]

Indicates support for the SB instruction in AArch32 state. Defined values are:

SBMeaning
0b0000

SB instruction is not implemented.

0b0001

SB instruction is implemented.

All other values are reserved.

ARMv8.0-SB implements the functionality identified by 0b0001.

From Armv8.5, the only permitted value is 0b0001.

FHM, bits [11:8]

Indicates support for Advanced SIMD and floating-point VFMAL and VFMSL instructions in AArch32 state. Defined values are:

FHMMeaning
0b0000

VFMAL and VMFSL instructions are not implemented.

0b0001

VFMAL and VMFSL instructions are implemented.

All other values are reserved.

ARMv8.2-FHM implements the functionality identified by 0b0001.

From Armv8.2, the permitted values are 0b0000 and 0b0001.

DP, bits [7:4]

Indicates support for Advanced SIMD and floating-point VFMAL and VFMSL instructions in AArch32 state. Defined values are:

DPMeaning
0b0000

Dot product instructions are not implemented.

0b0001

UDOT and VSDOT instructions are implemented.

All other values are reserved.

ARMv8.2-DotProd implements the functionality identified by 0b0001.

In Armv8.2, the permitted values are 0b0000 and 0b0001.

From Armv8.4, the only permitted value is 0b0001.

JSCVT, bits [3:0]

Indicates support for the VJCVT instruction in AArch32 state. Defined values are:

JSCVTMeaning
0b0000

The VJCVT instruction is not implemented.

0b0001

The VJCVT instruction is implemented.

All other values are reserved.

ARMv8.3-JSConv implements the functionality identified by 0b0001.

In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.

From Armv8.3, if Advanced SIMD or Floating-point is implemented, the only permitted value is 0b0001.

From Armv8.3, if Advanced SIMD or Floating-point is not implemented, the only permitted value is 0b0000.

Accessing the ID_ISAR6_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_ISAR6_EL1

op0op1CRnCRmop2
0b110b0000b00000b00100b111
if PSTATE.EL == EL0 then
    if IsFeatureImplemented("ARMv8.4-IDST") then
        if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_ISAR6_EL1) || boolean IMPLEMENTATION_DEFINED "ID_ISAR6_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_ISAR6_EL1;
elsif PSTATE.EL == EL2 then
    return ID_ISAR6_EL1;
elsif PSTATE.EL == EL3 then
    return ID_ISAR6_EL1;