AMCGCR, Activity Monitors Counter Group Configuration Register
The AMCGCR characteristics are:
Provides information on the number of activity monitor event counters implemented within each counter group.
External register AMCGCR bits [31:0] are architecturally mapped to AArch64 System register AMCGCR_EL0[31:0] .
External register AMCGCR bits [31:0] are architecturally mapped to AArch32 System register AMCGCR[31:0] .
The power domain of AMCGCR is IMPLEMENTATION DEFINED.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCGCR are RES0.
AMCGCR is a 32-bit register.
The AMCGCR bit assignments are:
CG1NC, bits [15:8]
Counter Group 1 Number of Counters. The number of counters in the auxiliary counter group.
In AMUv1, the permitted range of values is 0 to 16.
CG0NC, bits [7:0]
Counter Group 0 Number of Counters. The number of counters in the architected counter group.
In AMUv1, the value of this field is 4.
Accessing the AMCGCR
AMCGCR can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO.