CTIGATE, CTI Channel Gate Enable register
The CTIGATE characteristics are:
Determines whether events on channels propagate through the CTM to other ECT components, or from the CTM into the CTI.
CTIGATE is in the Debug power domain.
CTIGATE is a 32-bit register.
The CTIGATE bit assignments are:
|GATE<x>, bit [x]|
GATE<x>, bit [x], for x = 0 to 31
Channel <x> gate enable.
Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.
Disable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation.
Enable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation.
If GATE[x] is set to 0, no new events will be propagated to the ECT, and if the ECT supports multicycle channel events any existing output channel events will be terminated.
The following resets apply:
On a Cold reset, the value of this field is unchanged.
On an External debug reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Accessing the CTIGATE
CTIGATE can be accessed through the external debug interface:
This interface is accessible as follows:
- When SoftwareLockStatus() accesses to this register are RO.
- When !SoftwareLockStatus() accesses to this register are RW.