DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 - 15
The DBGBCR<n>_EL1 characteristics are:
Purpose
Holds control information for a breakpoint. Forms breakpoint n together with value register DBGBVR<n>_EL1.
Configuration
External register DBGBCR<n>_EL1 bits [31:0] are architecturally mapped to AArch64 System register DBGBCR<n>_EL1[31:0] .
External register DBGBCR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGBCR<n>[31:0] .
DBGBCR<n>_EL1 is in the Core power domain.
If breakpoint n is not implemented then accesses to this register are:
- RES0 when IsCorePowered() && !DoubleLockStatus() && !OSLockStatus() && AllowExternalDebugAccess().
- A CONSTRAINED UNPREDICTABLE choice of RES0 or ERROR otherwise.
Attributes
DBGBCR<n>_EL1 is a 32-bit register.
Field descriptions
The DBGBCR<n>_EL1 bit assignments are:
When the E field is zero, all the other fields in the register are ignored.
Bits [31:24]
Reserved, RES0.
BT, bits [23:20]
Breakpoint Type. Possible values are:
| BT | Meaning |
|---|---|
| 0b0000 |
Unlinked instruction address match. DBGBVR<n>_EL1 is the address of an instruction. |
| 0b0001 |
As 0b0000 but linked to a Context matching breakpoint. |
| 0b0010 |
Unlinked Context ID match. When ARMv8.1-VHE is implemented, EL2 is using AArch64, and the Effective value of HCR_EL2.E2H is 1, if either the PE is executing at EL0 with HCR_EL2.TGE set to 1 or the PE is executing at EL2, then DBGBVR<n>_EL1.ContextID must match the CONTEXTIDR_EL2 value. Otherwise, DBGBVR<n>_EL1.ContextID must match the CONTEXTIDR_EL1 value. |
| 0b0011 |
As 0b0010, with linking enabled. |
| 0b0100 |
Unlinked instruction address mismatch. DBGBVR<n>_EL1 is the address of an instruction to be stepped. |
| 0b0101 |
As 0b0100, with linking enabled. |
| 0b0110 |
Unlinked CONTEXTIDR_EL1 match. DBGBVR<n>_EL1.ContextID is a Context ID compared against CONTEXTIDR_EL1. |
| 0b0111 |
As 0b0110, with linking enabled. |
| 0b1000 |
Unlinked VMID match. DBGBVR<n>_EL1.VMID is a VMID compared against VTTBR_EL2.VMID. |
| 0b1001 |
As 0b1000, with linking enabled. |
| 0b1010 |
Unlinked VMID and Context ID match. DBGBVR<n>_EL1.ContextID is a Context ID compared against CONTEXTIDR_EL1, and DBGBVR<n>_EL1.VMID is a VMID compared against VTTBR_EL2.VMID. |
| 0b1011 |
As 0b1010, with linking enabled. |
| 0b1100 |
Unlinked CONTEXTIDR_EL2 match. DBGBVR<n>_EL1.ContextID2 is a Context ID compared against CONTEXTIDR_EL2. |
| 0b1101 |
As 0b1100, with linking enabled. |
| 0b1110 |
Unlinked Full Context ID match. DBGBVR<n>_EL1.ContextID is compared against CONTEXTIDR_EL1, and DBGBVR<n>_EL1.ContextID2 is compared against CONTEXTIDR_EL2. |
| 0b1111 |
As 0b1110, with linking enabled. |
Constraints on breakpoint programming mean some values are reserved under certain conditions.
For more information on the operation of the SSC, HMC, and PMC fields, and on the effect of programming this field to a reserved value, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' and 'Reserved DBGBCR<n>_EL1.BT values'.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
LBN, bits [19:16]
Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to.
For all other breakpoint types this field is ignored and reads of the register return an UNKNOWN value.
This field is ignored when the value of DBGBCR<n>_EL1.E is 0.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
SSC, bits [15:14]
Security state control. Determines the Security states under which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information, including the effect of programming the fields to a reserved set of values, see 'Reserved DBGBCR<n>_EL1.{SSC, HMC, PMC} values'.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
HMC, bit [13]
Higher mode control. Determines the debug perspective for deciding when a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see DBGBCR<n>_EL1.SSC description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Bits [12:9]
Reserved, RES0.
BAS, bits [8:5]
When AArch32 is supported at any Exception level:
When AArch32 is supported at any Exception level:
Byte address select. Defines which half-words an address-matching breakpoint matches, regardless of the instruction set and Execution state.
The permitted values depend on the breakpoint type.
For Address match breakpoints in either AArch32 or AArch64 state, the permitted values are:
| BAS | Match instruction at | Constraint for debuggers |
|---|---|---|
| 0b0011 | DBGBVR<n>_EL1 | Use for T32 instructions |
| 0b1100 | DBGBVR<n>_EL1 + 2 | Use for T32 instructions |
| 0b1111 | DBGBVR<n>_EL1 | Use for A64 and A32 instructions |
All other values are reserved.
For more information, see 'Using the BAS field in Address Match breakpoints'.
For Address mismatch breakpoints in an AArch32 stage 1 translation regime, the permitted values are:
| BAS | Match instruction at | Constraint for debuggers |
|---|---|---|
| 0b0000 | - | Use for a match anywhere breakpoint |
| 0b0011 | DBGBVR<n>_EL1 | Use for stepping T32 instructions |
| 0b1100 | DBGBVR<n>_EL1 + 2 | Use for stepping T32 instructions |
| 0b1111 | DBGBVR<n>_EL1 | Use for stepping A64 and A32 instructions |
For more information, see 'Using the BAS field in Address Match breakpoints'.
For Context matching breakpoints, this field is RES1 and ignored.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Otherwise:
Otherwise:
Reserved, RES1.
Bits [4:3]
Reserved, RES0.
PMC, bits [2:1]
Privilege mode control. Determines the Exception level or levels at which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the DBGBCR<n>_EL1.SSC description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
E, bit [0]
Enable breakpoint DBGBVR<n>_EL1. Possible values are:
| E | Meaning |
|---|---|
| 0b0 |
Breakpoint disabled. |
| 0b1 |
Breakpoint enabled. |
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Accessing the DBGBCR<n>_EL1
SoftwareLockStatus() depends on the type of access attempted and AllowExternalDebugAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
DBGBCR<n>_EL1 can be accessed through the external debug interface:
| Component | Offset | Instance |
|---|---|---|
| Debug | 0x408 + 16n | DBGBCR<n>_EL1 |
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalDebugAccess() and SoftwareLockStatus() accesses to this register are RO.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalDebugAccess() and !SoftwareLockStatus() accesses to this register are RW.
- Otherwise accesses to this register generate an error response.