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ERRERICR1, Error Recovery Interrupt Configuration Register 1

The ERRERICR1 characteristics are:

Purpose

Error Recovery Interrupt configuration register.

Configuration

This register is present only when the Error Recovery Interrupt is implemented and interrupt configuration registers use the recommended format. Otherwise, direct accesses to ERRERICR1 are IMPLEMENTATION DEFINED.

ERRERICR1 is implemented only as part of a memory-mapped group of error records.

Attributes

ERRERICR1 is a 32-bit register.

Field descriptions

The ERRERICR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
DATA

DATA, bits [31:0]

Payload for a message signaled interrupt.

The following resets apply:

  • On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the ERRERICR1

ERRERICR1 can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xE98

Accesses on this interface are RW.