ERRIIDR, Implementation Identification Register
The ERRIIDR characteristics are:
Defines the implementer of the component.
Implementation of this register is OPTIONAL.
This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERRIIDR are RES0.
ERRIIDR is a 32-bit register.
The ERRIIDR bit assignments are:
ProductID, bits [31:20]
Part number, bits [11:0]. The part number is selected by the designer of the component.
Variant, bits [19:16]
Component major revision.
This field distinguishes product variants or major revisions of the product.
Revision, bits [15:12]
Component minor revision.
This field distinguishes minor revisions of the product.
Implementer, bits [11:0]
Contains the JEP106 code of the company that implemented the RAS component. For an Arm implementation, this field has the value 0x43B.
Bits [11:8] contain the JEP106 continuation code of the implementer, and bits [6:0] contain the JEP106 identity code of the implementer. Bit 7 is RES0.
If ERRPIDR4 is implemented, ERRPIDR2 is implemented, and ERRPIDR1 is implemented, ERRPIDR4.DES_2 matches bits [11:8] of ERRIIDR.Implementer, ERRPIDR2.DES_1 matches bits [6:4] of ERRIIDR.Implementer, and ERRPIDR1.DES_0 matches bits [3:0] of ERRIIDR.Implementer.
Accessing the ERRIIDR
ERRIIDR can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO.