ERR<n>CTLR, Error Record Control Register, n = 0 - 65534
The ERR<n>CTLR characteristics are:
Purpose
The error control register contains enable bits for the node that writes to this record:
- Enabling error detection and correction.
- Enabling the critical error, error recovery, and fault handling interrupts.
- Enabling in-band error response for Uncorrected errors.
For each bit, if the selected node does not support the feature, then the bit is RES0. The definition of each record is IMPLEMENTATION DEFINED.
Configuration
This register is present only when error record <n> is implemented and error record <n> is the first error record owned by a node. Otherwise, direct accesses to ERR<n>CTLR are RES0.
ERR<n>FR describes the features implemented by the node.
Attributes
ERR<n>CTLR is a 64-bit register.
Field descriptions
The ERR<n>CTLR bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
| RES0 | CI | RES0 | WDUI | DUI | WCFI | CFI | WUE | WFI | WUI | UE | FI | UI | IMPLEMENTATION DEFINED | ED | |||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED, bits [63:32]
Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.
Bits [31:14]
Reserved, RES0.
CI, bit [13]
When ERR<n>FR.CI == 0b10:
When ERR<n>FR.CI == 0b10:
Critical error interrupt enable. When enabled, the critical error interrupt is generated for a critical error condition.
| CI | Meaning |
|---|---|
| 0b0 |
Critical error interrupt not generated for critical errors. Critical errors are treated as Uncontained errors. |
| 0b1 |
Critical error interrupt generated for critical errors. |
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bit [12]
Reserved, RES0.
WDUI, bit [11]
When ERR<n>FR.DUI == 0b11:
When ERR<n>FR.DUI == 0b11:
Error recovery interrupt for deferred errors on writes enable.
When enabled, the error recovery interrupt is generated for detected Deferred errors on writes.
| WDUI | Meaning |
|---|---|
| 0b0 |
Error recovery interrupt not generated for deferred errors on writes. |
| 0b1 |
Error recovery interrupt generated for deferred errors on writes. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
DUI, bit [10]
When ERR<n>FR.DUI == 0b10:
When ERR<n>FR.DUI == 0b10:
Error recovery interrupt for deferred errors enable.
When ERR<n>FR.DUI == 0b10, this control applies to errors arising from both reads and writes.
When enabled, the error recovery interrupt is generated for all detected Deferred errors.
| DUI | Meaning |
|---|---|
| 0b0 |
Error recovery interrupt not generated for deferred errors. |
| 0b1 |
Error recovery interrupt generated for deferred errors. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.DUI == 0b11:
When ERR<n>FR.DUI == 0b11:
Error recovery interrupt for deferred errors on reads enable.
When ERR<n>FR.DUI == 0b11, this bit is named RDUI.
When enabled, the error recovery interrupt is generated for detected Deferred errors on reads.
| RDUI | Meaning |
|---|---|
| 0b0 |
Error recovery interrupt not generated for deferred errors on reads. |
| 0b1 |
Error recovery interrupt generated for deferred errors on reads. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
WCFI, bit [9]
When ERR<n>FR.CFI == 0b11:
When ERR<n>FR.CFI == 0b11:
Fault handling interrupt for Corrected errors on writes enable.
When enabled:
- If the node implements Corrected error counters for writes, then the fault handling interrupt is generated when a counter overflows and the overflow bit for the counter is set to 0b1. For more information, see ERR<n>MISC0.
- Otherwise, the fault handling interrupt is also generated for detected Corrected errors onwrites.
| WCFI | Meaning |
|---|---|
| 0b0 |
Fault handling interrupt not generated for Corrected errors on writes. |
| 0b1 |
Fault handling interrupt generated for Corrected errors on writes. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
CFI, bit [8]
When ERR<n>FR.CFI == 0b10:
When ERR<n>FR.CFI == 0b10:
Fault handling interrupt for Corrected errors enable.
When ERR<n>FR.CFI == 0b10, this control applies to errors arising from both reads and writes.
When enabled:
- If the node implements Corrected error counters, then the fault handling interrupt is generated when a counter overflows and the overflow bit for the counter is set to 0b1. For more information, see ERR<n>MISC0.
- Otherwise, the fault handling interrupt is also generated for all detected Corrected errors.
| CFI | Meaning |
|---|---|
| 0b0 |
Fault handling interrupt not generated for Corrected errors. |
| 0b1 |
Fault handling interrupt generated for Corrected errors. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.CFI == 0b11:
When ERR<n>FR.CFI == 0b11:
Fault handling interrupt for Corrected errors on reads enable.
When ERR<n>FR.CFI == 0b11, this bit is named RCFI.
When enabled:
- If the node implements Corrected error counters for reads, then the fault handling interrupt is generated when a counter overflows and the overflow bit for the counter is set to 0b1. For more information, see ERR<n>MISC0.
- Otherwise, the fault handling interrupt is also generated for detected Corrected errors onreads.
| RCFI | Meaning |
|---|---|
| 0b0 |
Fault handling interrupt not generated for Corrected errors on reads. |
| 0b1 |
Fault handling interrupt generated for Corrected errors on reads. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
WUE, bit [7]
When ERR<n>FR.UE == 0b11:
When ERR<n>FR.UE == 0b11:
In-band Uncorrected error reporting on writes enable.
When enabled, responses to writes that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External Abort).
| WUE | Meaning |
|---|---|
| 0b0 |
External Abort response for Uncorrected errors on writes disabled. |
| 0b1 |
External Abort response for Uncorrected errors on writes enabled. |
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
WFI, bit [6]
When ERR<n>FR.FI == 0b11:
When ERR<n>FR.FI == 0b11:
Fault handling interrupt on writes enable.
When enabled:
- The fault handling interrupt is generated for detected Deferred errors and Uncorrected errors.
- If the corresponding fault handling interrupt for Corrected errors control is not implemented:
- If the node implements Corrected error counters for writes, then the fault handling interrupt is also generated when a counter overflows and the overflow bit for the counter is set to 0b1.
- Otherwise, the fault handling interrupt is also generated for detected Corrected errors on writes.
| WFI | Meaning |
|---|---|
| 0b0 |
Fault handling interrupt on writes disabled. |
| 0b1 |
Fault handling interrupt on writes enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
WUI, bit [5]
When ERR<n>FR.UI == 0b11:
When ERR<n>FR.UI == 0b11:
Uncorrected error recovery interrupt on writes enable.
When enabled, the error recovery interrupt is generated for detected Uncorrected errors on writes that are not deferred.
| WUI | Meaning |
|---|---|
| 0b0 |
Error recovery interrupt on writes disabled. |
| 0b1 |
Error recovery interrupt on writes enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
UE, bit [4]
When ERR<n>FR.UE == 0b10:
When ERR<n>FR.UE == 0b10:
In-band Uncorrected error reporting enable.
When ERR<n>FR.UE == 0b10, this control applies to errors arising from both reads and writes.
When enabled, responses to transactions that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External Abort).
| UE | Meaning |
|---|---|
| 0b0 |
External Abort response for Uncorrected errors disabled. |
| 0b1 |
External Abort response for Uncorrected errors enabled. |
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.UE == 0b11:
When ERR<n>FR.UE == 0b11:
In-band Uncorrected error reporting on reads enable.
When ERR<n>FR.UE == 0b11, this bit is named RUE.
When enabled, responses to reads that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External Abort).
| RUE | Meaning |
|---|---|
| 0b0 |
External Abort response for Uncorrected errors on reads disabled. |
| 0b1 |
External Abort response for Uncorrected errors on reads enabled. |
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
FI, bit [3]
When ERR<n>FR.FI == 0b10:
When ERR<n>FR.FI == 0b10:
Fault handling interrupt enable.
When ERR<n>FR.FI == 0b10, this control applies to errors arising from both reads and writes.
When enabled:
- The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors.
- If the fault handling interrupt for Corrected errors control is not implemented:
- If the node implements Corrected error counters, then the fault handling interrupt is also generated when a counter overflows and the overflow bit for the counter is set to 0b1.
- Otherwise, the fault handling interrupt is also generated for all detected Corrected errors.
| FI | Meaning |
|---|---|
| 0b0 |
Fault handling interrupt disabled. |
| 0b1 |
Fault handling interrupt enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.FI == 0b11:
When ERR<n>FR.FI == 0b11:
Fault handling interrupt on reads enable.
When ERR<n>FR.FI == 0b11, this bit is named RFI.
When enabled:
- The fault handling interrupt is generated for detected Deferred errors and Uncorrected errors.
- If the corresponding fault handling interrupt for Corrected errors control is not implemented:
- If the node implements Corrected error counters for reads, then the fault handling interrupt is also generated when a counter overflows and the overflow bit for the counter is set to 0b1.
- Otherwise, the fault handling interrupt is also generated for detected Corrected errors on reads.
| RFI | Meaning |
|---|---|
| 0b0 |
Fault handling interrupt on reads disabled. |
| 0b1 |
Fault handling interrupt on reads enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
UI, bit [2]
When ERR<n>FR.UI == 0b10:
When ERR<n>FR.UI == 0b10:
Uncorrected error recovery interrupt enable.
When ERR<n>FR.UI == 0b10, this control applies to errors arising from both reads and writes.
When enabled, the error recovery interrupt is generated for all detected Uncorrected errors that are not deferred.
| UI | Meaning |
|---|---|
| 0b0 |
Error recovery interrupt disabled. |
| 0b1 |
Error recovery interrupt enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.UI == 0b11:
When ERR<n>FR.UI == 0b11:
Uncorrected error recovery interrupt on reads enable.
When ERR<n>FR.UI == 0b11, this bit is named RUI.
When enabled, the error recovery interrupt is generated for detected Uncorrected errors on reads that are not deferred.
| RUI | Meaning |
|---|---|
| 0b0 |
Error recovery interrupt on reads disabled. |
| 0b1 |
Error recovery interrupt on reads enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
IMPLEMENTATION DEFINED, bit [1]
Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.
ED, bit [0]
When ERR<n>FR.ED == 0b10:
When ERR<n>FR.ED == 0b10:
Error reporting and logging enable. When disabled, the node behaves as if error detection and correction are disabled, and no errors are recorded or signaled by the node. Arm recommends that, when disabled, correct error detection and correction codes are written for writes, unless disabled by an IMPLEMENTATION DEFINED control for error injection.
| ED | Meaning |
|---|---|
| 0b0 |
Error reporting disabled. |
| 0b1 |
Error reporting enabled. |
It is IMPLEMENTATION DEFINED whether the node fully disables error detection and correction when reporting is disabled. That is, even with error reporting disabled, the node might continue to silently correct errors. Uncorrectable errors might result in corrupt data being silently propagated by the node.
If this node requires initialization after Cold reset to prevent signaling false errors, then Arm recommends this bit is set to 0b0 on Cold reset, meaning errors are not reported from Cold reset. This allows boot software to initialize a node without signaling errors. Software can enable error reporting after the node is initialized. Otherwise, the Cold reset value is IMPLEMENTATION DEFINED. If the Cold reset value is 0b1, the reset values of other controls in this register are also IMPLEMENTATION DEFINED and should not be UNKNOWN.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an IMPLEMENTATION DEFINED value.
Otherwise:
Otherwise:
Reserved, RES0.
Accessing the ERR<n>CTLR
ERR<n>CTLR can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| RAS | 0x008 + 64n | ERR<n>CTLR |
Accesses on this interface are RW.