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GICD_SETSPI_SR, Set Secure SPI Pending Register
The GICD_SETSPI_SR characteristics are:
Purpose
Adds the pending state to a valid SPI.
A write to this register changes the state of an inactive SPI to pending, and the state of an active SPI to active and pending.
Configuration
If GICD_TYPER.MBIS == 0, this register is reserved.
When GICD_CTLR.DS==1, this register is WI.
Attributes
GICD_SETSPI_SR is a 32-bit register.
Field descriptions
The GICD_SETSPI_SR bit assignments are:
Bits [31:13]
Reserved, RES0.
INTID, bits [12:0]
The INTID of the SPI.
The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt:
- For an edge-triggered interrupt, a write to GICD_SETSPI_NSR or GICD_SETSPI_SR adds the pending state to the targeted interrupt. It will stop being pending on activation, or if the pending state is removed by a write to GICD_CLRSPI_NSR, GICD_CLRSPI_SR, or GICD_ICPENDR<n>.
- For a level-sensitive interrupt, a write to GICD_SETSPI_NSR or GICD_SETSPI_SR adds the pending state to the targeted interrupt. It will remain pending until it is deasserted by a write to GICD_CLRSPI_NSR or GICD_CLRSPI_SR. If the interrupt is activated between having the pending state added and being deactivated, then the interrupt will be active and pending.
Accessing the GICD_SETSPI_SR
Writes to this register have no effect if:
- The value is written by a Non-secure access.
- The value written specifies an invalid SPI.
- The SPI is already pending.
16-bit accesses to bits [15:0] of this register must be supported.
GICD_SETSPI_SR can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Distributor | 0x0050 | GICD_SETSPI_SR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are WI.
- When IsAccessSecure() accesses to this register are WO.
- When !IsAccessSecure() accesses to this register are WI.