GICR_TYPER, Redistributor Type Register
The GICR_TYPER characteristics are:
Purpose
Provides information about the configuration of this Redistributor.
Configuration
A copy of this register is provided for each Redistributor.
Attributes
GICR_TYPER is a 64-bit register.
Field descriptions
The GICR_TYPER bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Affinity_Value | |||||||||||||||||||||||||||||||
PPInum | VSGI | CommonLPIAff | Processor_Number | RVPEID | MPAM | DPGS | Last | DirectLPI | Dirty | VLPIS | PLPIS | ||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Affinity_Value, bits [63:32]
The identity of the PE associated with this Redistributor.
Bits [63:56] provide Aff3, the Affinity level 3 value for the Redistributor.
Bits [55:48] provide Aff2, the Affinity level 2 value for the Redistributor.
Bits [47:40] provide Aff1, the Affinity level 1 value for the Redistributor.
Bits [39:32] provide Aff0, the Affinity level 0 value for the Redistributor.
PPInum, bits [31:27]
When GICv3.1 is implemented:
When GICv3.1 is implemented:
The value derived from this field specifies the maximum PPI INTID that a GIC implementation can support. An implementation might not implement all PPIs up to this maximum.
PPInum | Meaning |
---|---|
0b00000 |
Maximum PPI INTID is 31. |
0b00001 |
Maximum PPI INTID is 1087. |
0b00010 |
Maximum PPI INTID is 1119. |
All other values are reserved.
Otherwise:
Otherwise:
Reserved, RES0.
VSGI, bit [26]
When GICv4.1 is implemented:
When GICv4.1 is implemented:
Indicates whether vSGIs are supported.
VSGI | Meaning |
---|---|
0b0 |
Direct injection of SGIs not supported. |
0b1 |
Direct injection of SGIs supported. |
Otherwise:
Otherwise:
Reserved, RES0.
CommonLPIAff, bits [25:24]
The affinity level at which Redistributors share an LPI Configuration table.
CommonLPIAff | Meaning |
---|---|
0b00 |
All Redistributors must share an LPI Configuration table. |
0b01 |
All Redistributors with the same Aff3 value must share an LPI Configuration table. |
0b10 |
All Redistributors with the same Aff3.Aff2 value must share an LPI Configuration table. |
0b11 |
All Redistributors with the same Aff3.Aff2.Aff1 value must share an LPI Configuration table. |
Processor_Number, bits [23:8]
A unique identifier for the PE. When GITS_TYPER.PTA == 0, an ITS uses this field to identify the interrupt target.
When affinity routing is disabled for a Security state, this field indicates which GICD_ITARGETSR<n> corresponds to this Redistributor.
RVPEID, bit [7]
When GICv4.1 is implemented:
When GICv4.1 is implemented:
Indicates how the resident vPE is specified.
RVPEID | Meaning |
---|---|
0b0 |
GICR_VPENDBASER records the address of the vPE's Virtual Pending Table. |
0b1 |
GICR_VPENDBASER records vPEID. |
Otherwise:
Otherwise:
Reserved, RES0.
MPAM, bit [6]
When GICv3.1 is implemented:
When GICv3.1 is implemented:
MPAM
MPAM | Meaning |
---|---|
0b0 |
MPAM not supported. |
0b1 |
MPAM supported. |
Otherwise:
Otherwise:
Reserved, RES0.
DPGS, bit [5]
Sets support for GICR_CTLR.DPG* bits.
DPGS | Meaning |
---|---|
0b0 |
GICR_CTLR.DPG* bits are not supported. |
0b1 |
GICR_CTLR.DPG* bits are supported. |
Last, bit [4]
Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages.
Last | Meaning |
---|---|
0b0 |
This Redistributor is not the highest-numbered Redistributor in a series of contiguous Redistributor pages. |
0b1 |
This Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages. |
DirectLPI, bit [3]
Indicates whether this Redistributor supports direct injection of LPIs.
DirectLPI | Meaning |
---|---|
0b0 |
This Redistributor does not support direct injection of LPIs. The GICR_SETLPIR, GICR_CLRLPIR, GICR_INVLPIR, GICR_INVALLR, and GICR_SYNCR registers are either not implemented, or have an IMPLEMENTATION DEFINED purpose. |
0b1 |
This Redistributor supports direct injection of LPIs. The GICR_SETLPIR, GICR_CLRLPIR, GICR_INVLPIR, GICR_INVALLR, and GICR_SYNCR registers are implemented. |
Dirty, bit [2]
Controls the functionality of GICR_VPENDBASER.Dirty.
Dirty | Meaning |
---|---|
0b0 |
GICR_VPENDBASER.Dirty is UNKNOWN when GICR_VPENDBASER.Valid == 1. |
0b1 |
GICR_VPENDBASER.Dirty indicates when the Virtual Pending Table has been parsed when GICR_VPENDBASER.Valid is written from 0 to 1. |
When GICR_TYPER.VLPIS == 0, this field is RES0.
In GICv4.1 implementations this field is RES1.
VLPIS, bit [1]
Indicates whether the GIC implementation supports virtual LPIs and the direct injection of virtual LPIs.
VLPIS | Meaning |
---|---|
0b0 |
The implementation does not support virtual LPIs or the direct injection of virtual LPIs. |
0b1 |
The implementation supports virtual LPIs and the direct injection of virtual LPIs. |
In GICv3 implementations this field is RES0.
PLPIS, bit [0]
Indicates whether the GIC implementation supports physical LPIs.
PLPIS | Meaning |
---|---|
0b0 |
The implementation does not support physical LPIs. |
0b1 |
The implementation supports physical LPIs. |
Accessing the GICR_TYPER
GICR_TYPER can be accessed through the memory-mapped interfaces:
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | RD_base | 0x0008 | GICR_TYPER |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RO.
- When IsAccessSecure() accesses to this register are RO.
- When !IsAccessSecure() accesses to this register are RO.