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PMCIDR2, Performance Monitors Component Identification Register 2

The PMCIDR2 characteristics are:


Provides information to identify a Performance Monitor component.

For more information, see 'About the Component Identification scheme'.


Implementation of this register is OPTIONAL.

If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.


PMCIDR2 is a 32-bit register.

Field descriptions

The PMCIDR2 bit assignments are:


Bits [31:8]

Reserved, RES0.

PRMBL_2, bits [7:0]

Preamble. Must read as 0x05.

Accessing the PMCIDR2

PMCIDR2 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When ARMv8.3-DoPD is not implemented or IsCorePowered() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.