TRCAUXCTLR, Auxillary Control Register
The TRCAUXCTLR characteristics are:
Purpose
The function of this register is IMPLEMENTATION DEFINED.
Configuration
External register TRCAUXCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCAUXCTLR[31:0] .
This register is present only when ETE is implemented. Otherwise, direct accesses to TRCAUXCTLR are RES0.
Attributes
TRCAUXCTLR is a 32-bit register.
Field descriptions
The TRCAUXCTLR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED, bits [31:0]
IMPLEMENTATION_DEFINED.
This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.
On a Trace unit reset, this field resets to 0.
Accessing the TRCAUXCTLR
If this register is set to nonzero then it might cause the behavior of a trace unit to contradict this architecture specification. See the documentation of the specific implementation for information about the IMPLEMENTATION DEFINED support for this register.
TRCAUXCTLR can be accessed through the external debug interface:
| Component | Offset |
|---|---|
| ETE | 0x018 |
This interface is accessible as follows:
- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RW.