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TRCPIDR2, Peripheral Identification Register 2

The TRCPIDR2 characteristics are:


Provides discovery information about the component.

For additional information see the CoreSight Architecture Specification.


This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR2 are RES0.


TRCPIDR2 is a 32-bit register.

Field descriptions

The TRCPIDR2 bit assignments are:


Bits [31:8]

Reserved, RES0.

REVISION, bits [7:4]

Component major revision. TRCPIDR2.REVISION and TRCPIDR3.REVAND together form the revision number of the component, with TRCPIDR2.REVISION being the most significant part and TRCPIDR3.REVAND the least significant part. When a component is changed, TRCPIDR2.REVISION or TRCPIDR3.REVAND are increased to ensure that software can differentiate the different revisions of the component. If TRCPIDR2.REVISION is increased then TRCPIDR3.REVAND should be set to 0b0000.

This field reads as an IMPLEMENTATION DEFINED value.

JEDEC, bit [3]

JEDEC-assigned JEP106 implementer code is used.

This bit reads as one.

DES_1, bits [2:0]

Designer, JEP106 identification code, bits [6:4]. TRCPIDR1.DES_0 and TRCPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC

This field reads as an IMPLEMENTATION DEFINED value.


For a component designed by Arm Limited, the JEP106 identification code is 0x3B.

Accessing the TRCPIDR2

External debugger accesses to this register are unaffected by the OS Lock.

TRCPIDR2 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RO.