TRCSYNCPR, Synchronization Period Register

The TRCSYNCPR characteristics are:

Purpose

Controls how often trace protocol synchronization requests occur.

Configuration

External register TRCSYNCPR bits [31:0] are architecturally mapped to AArch64 System register TRCSYNCPR[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCSYNCPR are RES0.

Attributes

TRCSYNCPR is a 32-bit register.

Field descriptions

The TRCSYNCPR bit assignments are:

Bits [31:5]

Reserved, RES0.

PERIOD, bits [4:0]

Defines the number of bytes of trace between each periodic trace protocol synchronization request.

Other values are reserved. If a reserved value is programmed into PERIOD, then the behavior of the synchronization period counter is CONSTRAINED UNPREDICTABLE and one of the following behaviors occurs:

• No trace protocol synchronization requests are generated by this counter.
• Trace protocol synchronization requests occur at the specified period.
• Trace protocol synchronization requests occur at some other UNKNOWN period which can vary.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCSYNCPR

Must be programmed if TRCIDR3.SYNCPR == 0b0.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCSYNCPR can be accessed through the external debug interface:

This interface is accessible as follows:

• When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() accesses to this register generate an error response.
• Otherwise accesses to this register are RW.