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DLR, Debug Link Register
The DLR characteristics are:
Purpose
In Debug state, holds the address to restart from.
Configuration
AArch32 System register DLR bits [31:0] are architecturally mapped to AArch64 System register DLR_EL0[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DLR are UNDEFINED.
Attributes
DLR is a 32-bit register.
Field descriptions
The DLR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Restart address |
Bits [31:0]
Restart address.
Accessing the DLR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b011 | 0b0100 | 0b0101 | 0b001 |
if !Halted() then UNDEFINED; else return DLR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b011 | 0b0100 | 0b0101 | 0b001 |
if !Halted() then UNDEFINED; else DLR = R[t];