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DC CSW, Data or unified Cache line Clean by Set/Way

The DC CSW characteristics are:


Clean data cache by set/way.

When FEAT_MTE is implemented, this instruction might clean Allocation Tags from caches.


AArch64 System instruction DC CSW performs the same function as AArch32 System instruction DCCSW.


DC CSW is a 64-bit System instruction.

Field descriptions

The DC CSW input value bit assignments are:


Bits [63:32]

Reserved, RES0.

SetWay, bits [31:4]

Contains two fields:

  • Way, bits[31:32-A], the number of the way to operate on.
  • Set, bits[B-1:L], the number of the set to operate on.

Bits[L-1:4] are RES0.

A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = Log2(NSETS).

ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.

Level, bits [3:1]

Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache.

Bit [0]

Reserved, RES0.

Executing the DC CSW instruction

If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:

  • The instruction is UNDEFINED.
  • The instruction performs cache maintenance on one of:
    • No cache lines.
    • A single arbitrary cache line.
    • Multiple arbitrary cache lines.

Accesses to this instruction use the following encodings:

DC CSW, <Xt>

if PSTATE.EL == EL0 then
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.TSW == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCSW == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
elsif PSTATE.EL == EL2 then
elsif PSTATE.EL == EL3 then