DC CVAC, Data or unified Cache line Clean by VA to PoC
The DC CVAC characteristics are:
Purpose
Clean data cache by address to Point of Coherency.
When FEAT_MTE is implemented, this instruction might clean Allocation Tags from caches.
Configuration
AArch64 System instruction DC CVAC performs the same function as AArch32 System instruction DCCMVAC.
Attributes
DC CVAC is a 64-bit System instruction.
Field descriptions
The DC CVAC input value bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| Virtual address to use | |||||||||||||||||||||||||||||||
| Virtual address to use | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
Virtual address to use. No alignment restrictions apply to this VA.
Executing the DC CVAC instruction
If EL0 access is enabled, when executed at EL0, this instruction requires read access permission to the VA, otherwise it generates a Permission Fault, subject to the constraints described in 'Permission fault'.
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'.
Accesses to this instruction use the following encodings:
DC CVAC, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b011 | 0b0111 | 0b1010 | 0b001 |
if PSTATE.EL == EL0 then
if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.UCI == '0' then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && HCR_EL2.TPCP == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCVAC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.UCI == '0' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
DC_CVAC(X[t]);
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.TPCP == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCVAC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
DC_CVAC(X[t]);
elsif PSTATE.EL == EL2 then
DC_CVAC(X[t]);
elsif PSTATE.EL == EL3 then
DC_CVAC(X[t]);