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IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
The IC IALLUIS characteristics are:
Purpose
Invalidate all instruction caches in Inner Shareable domain to Point of Unification.
Configuration
AArch64 System instruction IC IALLUIS performs the same function as AArch32 System instruction ICIALLUIS.
Attributes
IC IALLUIS is a 64-bit System instruction.
Field descriptions
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
Executing the IC IALLUIS instruction
When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
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The instruction is UNDEFINED.
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The instruction behaves as if the Xt field is set to 0b11111.
Accesses to this instruction use the following encodings:
IC IALLUIS{, <Xt>}
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b0111 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TPU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TICAB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.ICIALLUIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else IC_IALLUIS(); elsif PSTATE.EL == EL2 then IC_IALLUIS(); elsif PSTATE.EL == EL3 then IC_IALLUIS();