TLBI VMALLE1IS, TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable
The TLBI VMALLE1IS characteristics are:
Purpose
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
-
The entry is a stage 1 translation table entry, from any level of the translation table walk.
-
When EL2 is implemented and enabled in the Security state described by the current value of SCR_EL3.NS:
-
When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate the specified VA using the EL1&0 translation regime.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
From Armv8.4, when a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:
- A PE with SCR_EL3.EEL2==1 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==0.
- A PE with SCR_EL3.EEL2==0 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==1.
- A PE is architecturally required to invalidate all relevant entries in the Secure EL1&0 translation of a System MMU in the same required shareability domain with a VMID of 0.
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
Configuration
There are no configuration notes.
Attributes
TLBI VMALLE1IS is a 64-bit System instruction.
Field descriptions
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
Executing the TLBI VMALLE1IS instruction
When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
-
The instruction is UNDEFINED.
-
The instruction behaves as if the Xt field is set to 0b11111.
Accesses to this instruction use the following encodings:
TLBI VMALLE1IS{, <Xt>}
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b1000 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIVMALLE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_VMALLE1IS(); elsif PSTATE.EL == EL2 then TLBI_VMALLE1IS(); elsif PSTATE.EL == EL3 then TLBI_VMALLE1IS();