AMCR_EL0, Activity Monitors Control Register
The AMCR_EL0 characteristics are:
Purpose
Global control register for the activity monitors implementation. AMCR_EL0 is applicable to both the architected and the auxiliary counter groups.
Configuration
AArch64 System register AMCR_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMCR[31:0] .
AArch64 System register AMCR_EL0 bits [31:0] are architecturally mapped to External register AMCR[31:0] .
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCR_EL0 are UNDEFINED.
Attributes
AMCR_EL0 is a 64-bit register.
Field descriptions
The AMCR_EL0 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | CG1RZ | RES0 | HDBG | RES0 | |||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:18]
Reserved, RES0.
CG1RZ, bit [17]
When FEAT_AMUv1p1 is implemented:
When FEAT_AMUv1p1 is implemented:
Counter Group 1 Read Zero.
| CG1RZ | Meaning |
|---|---|
| 0b0 |
System register reads of AMEVCNTR1<n>_EL0 return the event count at all implemented and enabled Exception levels. |
| 0b1 |
If the current Exception level is the highest implemented Exception level, system register reads of AMEVCNTR1<n>_EL0 return the event count. Otherwise, reads of AMEVCNTR1<n>_EL0 return a zero value. |
Reads from the memory-mapped view are unaffected by this field.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [16:11]
Reserved, RES0.
HDBG, bit [10]
This bit controls whether activity monitor counting is halted when the PE is halted in Debug state.
| HDBG | Meaning |
|---|---|
| 0b0 |
Activity monitors do not halt counting when the PE is halted in Debug state. |
| 0b1 |
Activity monitors halt counting when the PE is halted in Debug state. |
Bits [9:0]
Reserved, RES0.
Accessing the AMCR_EL0
Accesses to this register use the following encodings:
MRS <Xt>, AMCR_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1101 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then
UNDEFINED;
elsif AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TAM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMCR_EL0;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then
UNDEFINED;
elsif EL2Enabled() && CPTR_EL2.TAM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMCR_EL0;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then
UNDEFINED;
elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMCR_EL0;
elsif PSTATE.EL == EL3 then
return AMCR_EL0;
MSR AMCR_EL0, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1101 | 0b0010 | 0b000 |
if IsHighestEL(PSTATE.EL) then
AMCR_EL0 = X[t];
else
UNDEFINED;