CNTPS_CTL_EL1, Counter-timer Physical Secure Timer Control register
The CNTPS_CTL_EL1 characteristics are:
Purpose
Control register for the secure physical timer, usually accessible at EL3 but configurably accessible at EL1 in Secure state.
Configuration
There are no configuration notes.
Attributes
CNTPS_CTL_EL1 is a 64-bit register.
Field descriptions
The CNTPS_CTL_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | ISTATUS | IMASK | ENABLE | ||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:3]
Reserved, RES0.
ISTATUS, bit [2]
The status of the timer. This bit indicates whether the timer condition is met:
| ISTATUS | Meaning |
|---|---|
| 0b0 |
Timer condition is not met. |
| 0b1 |
Timer condition is met. |
When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
This bit is read-only.
IMASK, bit [1]
Timer interrupt mask bit. Permitted values are:
| IMASK | Meaning |
|---|---|
| 0b0 |
Timer interrupt is not masked by the IMASK bit. |
| 0b1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the ISTATUS bit.
This field resets to an architecturally UNKNOWN value.
ENABLE, bit [0]
Enables the timer. Permitted values are:
| ENABLE | Meaning |
|---|---|
| 0b0 |
Timer disabled. |
| 0b1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTPS_TVAL_EL1 continues to count down.
Disabling the output signal might be a power-saving option.
This field resets to an architecturally UNKNOWN value.
Accessing the CNTPS_CTL_EL1
Accesses to this register use the following encodings:
MRS <Xt>, CNTPS_CTL_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b111 | 0b1110 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && SCR_EL3.NS == '0' then
if SCR_EL3.EEL2 == '1' then
UNDEFINED;
elsif SCR_EL3.ST == '0' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return CNTPS_CTL_EL1;
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
return CNTPS_CTL_EL1;
MSR CNTPS_CTL_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b111 | 0b1110 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && SCR_EL3.NS == '0' then
if SCR_EL3.EEL2 == '1' then
UNDEFINED;
elsif SCR_EL3.ST == '0' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
CNTPS_CTL_EL1 = X[t];
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
CNTPS_CTL_EL1 = X[t];