DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 - 15
The DBGBCR<n>_EL1 characteristics are:
Purpose
Holds control information for a breakpoint. Forms breakpoint n together with value register DBGBVR<n>_EL1.
Configuration
AArch64 System register DBGBCR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGBCR<n>[31:0] .
AArch64 System register DBGBCR<n>_EL1 bits [31:0] are architecturally mapped to External register DBGBCR<n>_EL1[31:0] .
If breakpoint n is not implemented then accesses to this register are UNDEFINED.
Attributes
DBGBCR<n>_EL1 is a 64-bit register.
Field descriptions
The DBGBCR<n>_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | BT | LBN | SSC | HMC | RES0 | BAS | RES0 | PMC | E | ||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:24]
Reserved, RES0.
BT, bits [23:20]
Breakpoint Type. Possible values are:
BT | Meaning |
---|---|
0b0000 |
Unlinked instruction address match. DBGBVR<n>_EL1 is the address of an instruction. |
0b0001 |
As 0b0000, but linked to a Context matching breakpoint. |
0b0010 |
Unlinked Context ID match. When FEAT_VHE is implemented, EL2 is using AArch64, and the Effective value of HCR_EL2.E2H is 1, if either the PE is executing at EL0 with HCR_EL2.TGE set to 1 or the PE is executing at EL2, then DBGBVR<n>_EL1.ContextID must match the CONTEXTIDR_EL2 value. Otherwise, DBGBVR<n>_EL1.ContextID must match the CONTEXTIDR_EL1 value |
0b0011 |
As 0b0010, with linking enabled. |
0b0110 |
Unlinked CONTEXTIDR_EL1 match. DBGBVR<n>_EL1.ContextID is a Context ID compared against CONTEXTIDR_EL1. |
0b0111 |
As 0b0110, with linking enabled. |
0b1000 |
Unlinked VMID match. DBGBVR<n>_EL1.VMID is a VMID compared against VTTBR_EL2.VMID. |
0b1001 |
As 0b1000, with linking enabled. |
0b1010 |
Unlinked VMID and Context ID match. DBGBVR<n>_EL1.ContextID is a Context ID compared against CONTEXTIDR_EL1, and DBGBVR<n>_EL1.VMID is a VMID compared against VTTBR_EL2.VMID. |
0b1011 |
As 0b1010, with linking enabled. |
0b1100 |
Unlinked CONTEXTIDR_EL2 match. DBGBVR<n>_EL1.ContextID2 is a Context ID compared against CONTEXTIDR_EL2. |
0b1101 |
As 0b1100, with linking enabled. |
0b1110 |
Unlinked Full Context ID match. DBGBVR<n>_EL1.ContextID is compared against CONTEXTIDR_EL1, and DBGBVR<n>_EL1.ContextID2 is compared against CONTEXTIDR_EL2. |
0b1111 |
As 0b1110, with linking enabled. |
All other values are reserved. Constraints on breakpoint programming mean other values are reserved under some conditions.
For more information on the operation of the SSC, HMC, and PMC fields, and on the effect of programming this field to a reserved value, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' and 'Reserved DBGBCR<n>_EL1.BT values'.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
LBN, bits [19:16]
Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to.
For all other breakpoint types this field is ignored and reads of the register return an UNKNOWN value.
This field is ignored when the value of DBGBCR<n>_EL1.E is 0.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
SSC, bits [15:14]
Security state control. Determines the Security states under which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields.
For more information on the operation of the SSC, HMC, and PMC fields, and the effect of programming the fields to a reserved set of values, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' and 'Reserved DBGBCR<n>_EL1.{SSC, HMC, PMC} values'.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
HMC, bit [13]
Higher mode control. Determines the debug perspective for deciding when a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the SSC, bits [15:14] description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Bits [12:9]
Reserved, RES0.
BAS, bits [8:5]
When AArch32 is supported at any Exception level:
When AArch32 is supported at any Exception level:
Byte address select. Defines which half-words an address-matching breakpoint matches, regardless of the instruction set and Execution state.
The permitted values depend on the breakpoint type.
For Address match breakpoints, the permitted values are:
BAS | Match instruction at | Constraint for debuggers |
---|---|---|
0b0011 | DBGBVR<n>_EL1 | Use for T32 instructions |
0b1100 | DBGBVR<n>_EL1 + 2 | Use for T32 instructions |
0b1111 | DBGBVR<n>_EL1 | Use for A64 and A32 instructions |
All other values are reserved. For more information, see 'Reserved DBGBCR<n>_EL1.BAS values'.
For more information on using the BAS field in address match breakpoints, see 'Using the BAS field in Address Match breakpoints'.
For Context matching breakpoints, this field is RES1 and ignored.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Otherwise:
Otherwise:
Reserved, RES1.
Bits [4:3]
Reserved, RES0.
PMC, bits [2:1]
Privilege mode control. Determines the Exception level or levels at which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the DBGBCR<n>_EL1.SSC description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
E, bit [0]
Enable breakpoint DBGBVR<n>_EL1.
E | Meaning |
---|---|
0b0 |
Breakpoint disabled. |
0b1 |
Breakpoint enabled. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Accessing the DBGBCR<n>_EL1
Accesses to this register use the following encodings:
MRS <Xt>, DBGBCR<n>_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b0000 | n[3:0] | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.DBGBCRn_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBCR_EL1[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBCR_EL1[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL3 then if OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBCR_EL1[UInt(CRm<3:0>)];
MSR DBGBCR<n>_EL1, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b0000 | n[3:0] | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.DBGBCRn_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBCR_EL1[UInt(CRm<3:0>)] = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBCR_EL1[UInt(CRm<3:0>)] = X[t]; elsif PSTATE.EL == EL3 then if OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBCR_EL1[UInt(CRm<3:0>)] = X[t];