ICV_DIR_EL1, Interrupt Controller Deactivate Virtual Interrupt Register
The ICV_DIR_EL1 characteristics are:
Purpose
When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified virtual interrupt.
Configuration
AArch64 System register ICV_DIR_EL1 bits [31:0] performs the same function as AArch32 System register ICV_DIR[31:0] .
Attributes
ICV_DIR_EL1 is a 64-bit register.
Field descriptions
The ICV_DIR_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | INTID | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:24]
Reserved, RES0.
INTID, bits [23:0]
The INTID of the virtual interrupt to be deactivated.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR_EL1.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
Accessing the ICV_DIR_EL1
When EOImode == 0, writes are ignored. In systems supporting system error generation, an implementation might generate an SEI.
Accesses to this register use the following encodings:
MSR ICC_DIR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1100 | 0b1011 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.<IRQ,FIQ> == '11' then
UNDEFINED;
elsif ICC_SRE_EL1.SRE == '0' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && ICH_HCR_EL2.TDIR == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && ICH_HCR_EL2.TC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.FMO == '1' then
ICV_DIR_EL1 = X[t];
elsif EL2Enabled() && HCR_EL2.IMO == '1' then
ICV_DIR_EL1 = X[t];
elsif HaveEL(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
ICC_DIR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.<IRQ,FIQ> == '11' then
UNDEFINED;
elsif ICC_SRE_EL2.SRE == '0' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
ICC_DIR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
if ICC_SRE_EL3.SRE == '0' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
ICC_DIR_EL1 = X[t];