You copied the Doc URL to your clipboard.

ID_AA64ZFR0_EL1, SVE Feature ID register 0

The ID_AA64ZFR0_EL1 characteristics are:

Purpose

Provides additional information about the implemented features of the AArch64 Scalable Vector Extension, when the ID_AA64PFR0_EL1.SVE field is not zero.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.

Configuration

Note

Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Attributes

ID_AA64ZFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64ZFR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0F64MMF32MMRES0I8MMSM4RES0SHA3
RES0BF16BitPermRES0AESSVEver
313029282726252423222120191817161514131211109876543210

Bits [63:60]

Reserved, RES0.

F64MM, bits [59:56]

Indicates support for SVE FP64 double-precision floating-point matrix multiplication instructions. Defined values are:

F64MMMeaning
0b0000

FP64 matrix multiplication and related instructions are not implemented.

0b0001

FP64 variant of the FMMLA instruction, and LD1RO* instructions are implemented. The 128-bit element variations of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2 are also implemented.

All other values are reserved.

FEAT_F64MM implements the functionality identified by 0b0001.

From Armv8.2, the permitted values are 0b0000 and 0b0001.

F32MM, bits [55:52]

Indicates support for the SVE FP32 single-precision floating-point matrix multiplication instruction. Defined values are:

F32MMMeaning
0b0000

FP32 matrix multiplication instruction is not implemented.

0b0001

FP32 variant of the FMMLA instruction is implemented.

All other values are reserved.

FEAT_F32MM implements the functionality identified by 0b0001.

From Arm v8.2, the permitted values are 0b0000 and 0b0001.

Bits [51:48]

Reserved, RES0.

I8MM, bits [47:44]

Indicates support for SVE Int8 matrix multiplication instructions. Defined values are:

I8MMMeaning
0b0000

Int8 matrix multiplication instructions are not implemented.

0b0001

SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented.

All other values are reserved.

FEAT_I8MM implements the functionality identified by 0b0001.

When Advanced SIMD and SVE are both implemented, this field must return the same value as ID_AA64ISAR1_EL1.I8MM.

From Armv8.6, the only permitted value is 0b0001.

SM4, bits [43:40]

Indicates support for SVE SM4 instructions. Defined values are:

SM4Meaning
0b0000

SVE SM4 instructions are not implemented.

0b0001

SVE SM4E and SM4EKEY instructions are implemented.

All other values are reserved.

FEAT_SVE_SM4 implements the functionality identified by 0b0001.

Bits [39:36]

Reserved, RES0.

SHA3, bits [35:32]

Indicates support for the SVE SHA3 instructions. Defined values are:

SHA3Meaning
0b0000

SVE SHA3 instructions are not implemented.

0b0001

SVE RAX1 instruction is implemented.

All other values are reserved.

FEAT_SVE_SHA3 implements the functionality identified by 0b0001.

Bits [31:24]

Reserved, RES0.

BF16, bits [23:20]

Indicates support for SVE BFloat16 instructions. Defined values are:

BF16Meaning
0b0000

BFloat16 instructions are not implemented.

0b0001

BFCVT, BFCVTNT, BFDOT, BFMLALB, BFMLALT, and BFMMLA instructions are implemented.

All other values are reserved.

FEAT_BF16 implements the functionality identified by 0b0001.

When Advanced SIMD and SVE are both implemented, this field must return the same value as ID_AA64ISAR1_EL1.BF16.

From ARMv8.6, the only permitted value is 0b0001.

BitPerm, bits [19:16]

Indicates support for SVE bit permute instructions. Defined values are:

BitPermMeaning
0b0000

SVE bit permute instructions are not implemented.

0b0001

SVE BDEP, BEXT and BGRP instructions are implemented.

All other values are reserved.

FEAT_SVE_BitPerm implements the functionality identified by 0b0001.

Bits [15:8]

Reserved, RES0.

AES, bits [7:4]

Indicates support for SVE AES instructions. Defined values are:

AESMeaning
0b0000

SVE AES instructions are not implemented.

0b0001

SVE AESE, AESD, AESMC and AESIMC instructions are implemented.

0b0010

As 0b0001, plus SVE PMULLB and PMULLT instructions with 64-bit source.

All other values are reserved.

The permitted values are 0b0000 and 0b0010.

SVEver, bits [3:0]

Scalable Vector Extension instruction set version. Defined values are:

SVEverMeaning
0b0000

SVE instructions are implemented.

0b0001

SVE and the non-optional SVE2 instructions are implemented.

All other values are reserved. This field is only valid if the ID_AA64PFR0_EL1.SVE field is not zero.

Accessing the ID_AA64ZFR0_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_AA64ZFR0_EL1

op0op1CRnCRmop2
0b110b0000b00000b01000b100
if PSTATE.EL == EL0 then
    if IsFeatureImplemented("FEAT_IDST") then
        if EL2Enabled() && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && (!IsZero(ID_AA64ZFR0_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64ZFR0_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_AA64ZFR0_EL1;
elsif PSTATE.EL == EL2 then
    return ID_AA64ZFR0_EL1;
elsif PSTATE.EL == EL3 then
    return ID_AA64ZFR0_EL1;